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Commit ab31c4c4 authored by Sana Venkat Raju's avatar Sana Venkat Raju
Browse files

ARM: dts: msm: Configure SPI on BLSP1 QUP6 for 8909 



Configure SPI on BLSP1-QUP6.

Change-Id: Icc30be2e84e530e9de4312f352ea4bace6e5663f
Signed-off-by: default avatarSana Venkat Raju <c_vsana@codeaurora.org>
parent aab7a0ec

arch/arm/boot/dts/qcom/msmferrum-pinctrl.dtsi

+50 −0
Original line number Diff line number Diff line
@@ -149,5 +149,55 @@ 
				drive-strength = <2>; /* 2 MA */

			};

		};

		spi0_active {

                        /* MOSI, MISO, CLK */

                        qcom,pins = <&gp 8>, <&gp 9>, <&gp 11>;

                        qcom,num-grp-pins = <3>;

                        qcom,pin-func = <1>;

                        label = "spi0-active";

                        /* active state */

                        spi0_default: default {

                                drive-strength = <12>; /* 12 MA */

                                bias-disable = <0>; /* No PULL */

                        };

                };



                spi0_suspend {

                        /* MOSI, MISO, CLK */

                        qcom,pins = <&gp 8>, <&gp 9>, <&gp 11>;

                        qcom,num-grp-pins = <3>;

                        qcom,pin-func = <0>;

                        label = "spi0-suspend";

                        /* suspended state */

                        spi0_sleep: sleep {

                                drive-strength = <2>; /* 2 MA */

                                bias-pull-down; /* pull down */

                        };

                };

                spi0_cs0_active {

                        /* CS */

                        qcom,pins = <&gp 10>;

                        qcom,num-grp-pins = <1>;

                        qcom,pin-func = <1>;

                        label = "spi0-cs0-active";

                        spi0_cs0_active: cs0_active {

                                drive-strength = <2>;

                                bias-disable = <0>;

                        };

                };





                spi0_cs0_suspend {

                        /* CS */

                        qcom,pins = <&gp 10>;

                        qcom,num-grp-pins = <1>;

                        qcom,pin-func = <0>;

                        label = "spi0-cs0-suspend";

                        spi0_cs0_sleep: cs0_sleep {

                                drive-strength = <2>;

                                bias-disable = <0>;

                        };

                };



	};

};

arch/arm/boot/dts/qcom/msmferrum.dtsi

+27 −0
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ 


		sdhc1 = &sdhc_1; /* SDC1 eMMC slot */

		sdhc2 = &sdhc_2; /* SDC2 SD card slot */

		spi0 = &spi_0; /* SPI0 controller device */

	};



	cpus {
@@ -476,6 +477,32 @@ 


		status = "disabled";

	};

	spi_0: spi@78ba000 { /* BLSP1 QUP6 */

                compatible = "qcom,spi-qup-v2";

                #address-cells = <1>;

                #size-cells = <0>;

                reg-names = "spi_physical", "spi_bam_physical";

                reg = <0x78ba000 0x600>,

                      <0x7884000 0x23000>;

                interrupt-names = "spi_irq", "spi_bam_irq";

                interrupts = <0 100 0>, <0 238 0>;

                spi-max-frequency = <19200000>;

                pinctrl-names = "default", "sleep";

                pinctrl-0 = <&spi0_default &spi0_cs0_active>;

                pinctrl-1 = <&spi0_sleep &spi0_cs0_sleep>;

                clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,

                         <&clock_gcc clk_gcc_blsp1_qup6_spi_apps_clk>;

                clock-names = "iface_clk", "core_clk";

                qcom,infinite-mode = <0>;

                qcom,use-bam;

                qcom,use-pinctrl;

                qcom,ver-reg-exists;

                qcom,bam-consumer-pipe-index = <14>;

                qcom,bam-producer-pipe-index = <15>;

                qcom,master-id = <86>;

	};





};



#include "msmferrum-regulator.dtsi"