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Commit aa6d1d5b authored by AnilKumar Chimata's avatar AnilKumar Chimata
Browse files

ARM: dts: msm: Update qcrypto flags for msm8916 and msm8939 



Update qcrypto driver flags to enable aes-cbc, ecb, ctr, ccm xts
and hash algorithms.

Change-Id: Ifade8fd638f87fc13c678adcc17c054ba50482ab
Signed-off-by: default avatarAnilKumar Chimata <anilc@codeaurora.org>
parent bf6a4fa8

arch/arm/boot/dts/qcom/msm8916.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -683,6 +683,7 @@ 
				"iface_clk", "bus_clk";

		qcom,use-sw-aes-cbc-ecb-ctr-algo;

		qcom,use-sw-aes-xts-algo;

		qcom,use-sw-aes-ccm-algo;

		qcom,use-sw-ahash-algo;

		status = "disabled";

		qcom,ce-opp-freq = <100000000>;

arch/arm/boot/dts/qcom/msm8939-common.dtsi

+4 −1
Original line number Diff line number Diff line
@@ -669,7 +669,6 @@ 
		qcom,bam-pipe-pair = <2>;

		qcom,ce-hw-instance = <0>;

		qcom,ce-device = <0>;

		qcom,ce-hw-shared;

		qcom,msm-bus,name = "qcrypto-noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;
@@ -682,6 +681,10 @@ 
			 <&clock_gcc clk_gcc_crypto_axi_clk>;

		clock-names = "core_clk_src", "core_clk",

				"iface_clk", "bus_clk";

                qcom,use-sw-aes-cbc-ecb-ctr-algo;

                qcom,use-sw-aes-xts-algo;

                qcom,use-sw-aes-ccm-algo;

                qcom,use-sw-ahash-algo;

		status = "disabled";

		qcom,ce-opp-freq = <100000000>;

	};