Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a94c9a07 authored by Azhar Shaikh's avatar Azhar Shaikh
Browse files

usb: dwc3: Update the wait times in dwc3_core_and_phy_soft_reset() 



In the current code, wait times between PHY resets in
dwc3_core_and_phy_soft_reset() is not as per Hardware Programming Guide.
Update these values as per Hardware Programming Guide.

Change-Id: Ib86a2fde25b9305cf3633bcb43fc5afc80234a50
Signed-off-by: default avatarAzhar Shaikh <azhars@codeaurora.org>
parent 93974768

drivers/usb/dwc3/core.c

+4 −4
Original line number Diff line number Diff line
@@ -153,7 +153,7 @@ static void dwc3_core_and_phy_soft_reset(struct dwc3 *dwc) 
	reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;

	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);



	msleep(100);

	usleep_range(1000, 1200);



	/* Clear USB3 PHY reset */

	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
@@ -171,21 +171,21 @@ static void dwc3_core_and_phy_soft_reset(struct dwc3 *dwc) 
	reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;

	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);



	msleep(100);

	usleep_range(1000, 1200);



	/* Clear USB2 PHY reset */

	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));

	reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;

	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);



	msleep(100);

	usleep_range(200, 500);



	/* After PHYs are stable we can take Core out of reset state */

	reg = dwc3_readl(dwc->regs, DWC3_GCTL);

	reg &= ~DWC3_GCTL_CORESOFTRESET;

	dwc3_writel(dwc->regs, DWC3_GCTL, reg);



	msleep(100);

	usleep_range(1000, 1200);

}



/**