Loading arch/arm/boot/dts/qcom/apq8084-gpu.dtsi +6 −1 Original line number Diff line number Diff line Loading @@ -27,7 +27,12 @@ qcom,idle-timeout = <8>; //<HZ/12> qcom,strtstp-sleepwake; qcom,clk-map = <0x00000006>; //KGSL_CLK_CORE | KGSL_CLK_IFACE /* * Clocks = KGSL_CLK_CORE | KGSL_CLK_IFACE | * KGSL_CLK_RBBMTIMER */ qcom,clk-map = <0x00000086>; /* Bus Scale Settings */ qcom,bus-control; Loading arch/arm/mach-msm/clock-8084.c +2 −1 Original line number Diff line number Diff line Loading @@ -6544,7 +6544,8 @@ static struct clk_lookup apq_clocks_8084[] = { "fdd00000.qcom,ocmem"), CLK_LOOKUP("core_clk", oxili_gfx3d_clk.c, "fdb00000.qcom,kgsl-3d0"), CLK_LOOKUP("iface_clk", oxilicx_ahb_clk.c, "fdb00000.qcom,kgsl-3d0"), CLK_LOOKUP("", oxili_rbbmtimer_clk.c, ""), CLK_LOOKUP("rbbmtimer_clk", oxili_rbbmtimer_clk.c, "fdb00000.qcom,kgsl-3d0"), CLK_LOOKUP("", venus0_ahb_clk.c, ""), CLK_LOOKUP("", venus0_axi_clk.c, ""), Loading drivers/gpu/msm/kgsl_pwrctrl.c +10 −2 Original line number Diff line number Diff line Loading @@ -72,6 +72,10 @@ static struct clk_pair clks[KGSL_MAX_CLKS] = { .name = "alt_mem_iface_clk", .map = KGSL_CLK_ALT_MEM_IFACE, }, { .name = "rbbmtimer_clk", .map = KGSL_CLK_RBBMTIMER, }, }; static void kgsl_pwrctrl_axi(struct kgsl_device *device, int state); Loading Loading @@ -925,7 +929,7 @@ EXPORT_SYMBOL(kgsl_pwrctrl_irq); int kgsl_pwrctrl_init(struct kgsl_device *device) { int i, k, m, n = 0, result = 0; unsigned int freq_i; unsigned int freq_i, rbbmtimer_freq; struct clk *clk; struct platform_device *pdev = container_of(device->parentdev, struct platform_device, dev); Loading Loading @@ -976,9 +980,13 @@ int kgsl_pwrctrl_init(struct kgsl_device *device) pdata->pwrlevel[i].io_fraction; } /* Do not set_rate for targets in sync with AXI */ if (pwr->pwrlevels[0].gpu_freq > 0) if (pwr->pwrlevels[0].gpu_freq > 0) { clk_set_rate(pwr->grp_clks[0], pwr-> pwrlevels[pwr->num_pwrlevels - 1].gpu_freq); rbbmtimer_freq = clk_round_rate(pwr->grp_clks[6], KGSL_RBBMTIMER_CLK_FREQ); clk_set_rate(pwr->grp_clks[6], rbbmtimer_freq); } pwr->gpu_reg = regulator_get(&pdev->dev, "vdd"); if (IS_ERR(pwr->gpu_reg)) Loading drivers/gpu/msm/kgsl_pwrctrl.h +3 −1 Original line number Diff line number Diff line Loading @@ -25,11 +25,13 @@ #define KGSL_PWR_ON 0xFFFF #define KGSL_MAX_CLKS 6 #define KGSL_MAX_CLKS 7 /* Only two supported levels, min & max */ #define KGSL_CONSTRAINT_PWR_MAXLEVELS 2 #define KGSL_RBBMTIMER_CLK_FREQ 19200000 struct platform_device; struct kgsl_clk_stats { Loading include/linux/msm_kgsl.h +1 −0 Original line number Diff line number Diff line Loading @@ -11,6 +11,7 @@ #define KGSL_CLK_MEM_IFACE 0x00000010 #define KGSL_CLK_AXI 0x00000020 #define KGSL_CLK_ALT_MEM_IFACE 0x00000040 #define KGSL_CLK_RBBMTIMER 0x00000080 #define KGSL_MAX_PWRLEVELS 10 Loading Loading
arch/arm/boot/dts/qcom/apq8084-gpu.dtsi +6 −1 Original line number Diff line number Diff line Loading @@ -27,7 +27,12 @@ qcom,idle-timeout = <8>; //<HZ/12> qcom,strtstp-sleepwake; qcom,clk-map = <0x00000006>; //KGSL_CLK_CORE | KGSL_CLK_IFACE /* * Clocks = KGSL_CLK_CORE | KGSL_CLK_IFACE | * KGSL_CLK_RBBMTIMER */ qcom,clk-map = <0x00000086>; /* Bus Scale Settings */ qcom,bus-control; Loading
arch/arm/mach-msm/clock-8084.c +2 −1 Original line number Diff line number Diff line Loading @@ -6544,7 +6544,8 @@ static struct clk_lookup apq_clocks_8084[] = { "fdd00000.qcom,ocmem"), CLK_LOOKUP("core_clk", oxili_gfx3d_clk.c, "fdb00000.qcom,kgsl-3d0"), CLK_LOOKUP("iface_clk", oxilicx_ahb_clk.c, "fdb00000.qcom,kgsl-3d0"), CLK_LOOKUP("", oxili_rbbmtimer_clk.c, ""), CLK_LOOKUP("rbbmtimer_clk", oxili_rbbmtimer_clk.c, "fdb00000.qcom,kgsl-3d0"), CLK_LOOKUP("", venus0_ahb_clk.c, ""), CLK_LOOKUP("", venus0_axi_clk.c, ""), Loading
drivers/gpu/msm/kgsl_pwrctrl.c +10 −2 Original line number Diff line number Diff line Loading @@ -72,6 +72,10 @@ static struct clk_pair clks[KGSL_MAX_CLKS] = { .name = "alt_mem_iface_clk", .map = KGSL_CLK_ALT_MEM_IFACE, }, { .name = "rbbmtimer_clk", .map = KGSL_CLK_RBBMTIMER, }, }; static void kgsl_pwrctrl_axi(struct kgsl_device *device, int state); Loading Loading @@ -925,7 +929,7 @@ EXPORT_SYMBOL(kgsl_pwrctrl_irq); int kgsl_pwrctrl_init(struct kgsl_device *device) { int i, k, m, n = 0, result = 0; unsigned int freq_i; unsigned int freq_i, rbbmtimer_freq; struct clk *clk; struct platform_device *pdev = container_of(device->parentdev, struct platform_device, dev); Loading Loading @@ -976,9 +980,13 @@ int kgsl_pwrctrl_init(struct kgsl_device *device) pdata->pwrlevel[i].io_fraction; } /* Do not set_rate for targets in sync with AXI */ if (pwr->pwrlevels[0].gpu_freq > 0) if (pwr->pwrlevels[0].gpu_freq > 0) { clk_set_rate(pwr->grp_clks[0], pwr-> pwrlevels[pwr->num_pwrlevels - 1].gpu_freq); rbbmtimer_freq = clk_round_rate(pwr->grp_clks[6], KGSL_RBBMTIMER_CLK_FREQ); clk_set_rate(pwr->grp_clks[6], rbbmtimer_freq); } pwr->gpu_reg = regulator_get(&pdev->dev, "vdd"); if (IS_ERR(pwr->gpu_reg)) Loading
drivers/gpu/msm/kgsl_pwrctrl.h +3 −1 Original line number Diff line number Diff line Loading @@ -25,11 +25,13 @@ #define KGSL_PWR_ON 0xFFFF #define KGSL_MAX_CLKS 6 #define KGSL_MAX_CLKS 7 /* Only two supported levels, min & max */ #define KGSL_CONSTRAINT_PWR_MAXLEVELS 2 #define KGSL_RBBMTIMER_CLK_FREQ 19200000 struct platform_device; struct kgsl_clk_stats { Loading
include/linux/msm_kgsl.h +1 −0 Original line number Diff line number Diff line Loading @@ -11,6 +11,7 @@ #define KGSL_CLK_MEM_IFACE 0x00000010 #define KGSL_CLK_AXI 0x00000020 #define KGSL_CLK_ALT_MEM_IFACE 0x00000040 #define KGSL_CLK_RBBMTIMER 0x00000080 #define KGSL_MAX_PWRLEVELS 10 Loading