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Commit a7039bd6 authored by Lennert Buytenhek's avatar Lennert Buytenhek Committed by Nicolas Pitre
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[ARM] feroceon: remove CONFIG_CPU_DCACHE_WRITETHROUGH check 



Since the Feroceon doesn't have a global WT override bit like
ARM926 does, remove all code relating to this mode of operation
from proc-feroceon.S.

Signed-off-by: default avatarLennert Buytenhek <buytenh@marvell.com>
Signed-off-by: default avatarNicolas Pitre <nico@marvell.com>
parent a3fd133c

arch/arm/mm/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -658,7 +658,7 @@ config CPU_DCACHE_SIZE 


config CPU_DCACHE_WRITETHROUGH

	bool "Force write through D-cache"

	depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FEROCEON) && !CPU_DCACHE_DISABLE

	depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE

	default y if CPU_ARM925T

	help

	  Say Y here to use the data cache in writethrough mode. Unless you

arch/arm/mm/proc-feroceon.S

+0 −40
Original line number Diff line number Diff line
@@ -118,12 +118,8 @@ ENTRY(feroceon_flush_kern_cache_all) 
	mov	r2, #VM_EXEC

	mov	ip, #0

__flush_whole_cache:

#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH

	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache

#else

1:	mrc	p15, 0, r15, c7, c14, 3 	@ test,clean,invalidate

	bne	1b

#endif

	tst	r2, #VM_EXEC

	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache

	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
@@ -145,21 +141,12 @@ ENTRY(feroceon_flush_user_cache_range) 
	cmp	r3, #CACHE_DLIMIT

	bgt	__flush_whole_cache

1:	tst	r2, #VM_EXEC

#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH

	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry

	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry

	add	r0, r0, #CACHE_DLINESIZE

	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry

	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry

	add	r0, r0, #CACHE_DLINESIZE

#else

	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry

	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry

	add	r0, r0, #CACHE_DLINESIZE

	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry

	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry

	add	r0, r0, #CACHE_DLINESIZE

#endif

	cmp	r0, r1

	blo	1b

	tst	r2, #VM_EXEC
@@ -232,12 +219,10 @@ ENTRY(feroceon_flush_kern_dcache_page) 
 * (same as v4wb)

 */

ENTRY(feroceon_dma_inv_range)

#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH

	tst	r0, #CACHE_DLINESIZE - 1

	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry

	tst	r1, #CACHE_DLINESIZE - 1

	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry

#endif

	bic	r0, r0, #CACHE_DLINESIZE - 1

1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry

	add	r0, r0, #CACHE_DLINESIZE
@@ -257,13 +242,11 @@ ENTRY(feroceon_dma_inv_range) 
 * (same as v4wb)

 */

ENTRY(feroceon_dma_clean_range)

#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH

	bic	r0, r0, #CACHE_DLINESIZE - 1

1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry

	add	r0, r0, #CACHE_DLINESIZE

	cmp	r0, r1

	blo	1b

#endif

	mcr	p15, 0, r0, c7, c10, 4		@ drain WB

	mov	pc, lr
@@ -278,11 +261,7 @@ ENTRY(feroceon_dma_clean_range) 
ENTRY(feroceon_dma_flush_range)

	bic	r0, r0, #CACHE_DLINESIZE - 1

1:

#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH

	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry

#else

	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry

#endif

	add	r0, r0, #CACHE_DLINESIZE

	cmp	r0, r1

	blo	1b
@@ -301,12 +280,10 @@ ENTRY(feroceon_cache_fns) 
	.long	feroceon_dma_flush_range



ENTRY(cpu_feroceon_dcache_clean_area)

#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH

1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry

	add	r0, r0, #CACHE_DLINESIZE

	subs	r1, r1, #CACHE_DLINESIZE

	bhi	1b

#endif

	mcr	p15, 0, r0, c7, c10, 4		@ drain WB

	mov	pc, lr
@@ -323,13 +300,9 @@ ENTRY(cpu_feroceon_dcache_clean_area) 
ENTRY(cpu_feroceon_switch_mm)

#ifdef CONFIG_MMU

	mov	ip, #0

#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH

	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache

#else

@ && 'Clean & Invalidate whole DCache'

1:	mrc	p15, 0, r15, c7, c14, 3 	@ test,clean,invalidate

	bne	1b

#endif

	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache

	mcr	p15, 0, ip, c7, c10, 4		@ drain WB

	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
@@ -362,16 +335,9 @@ ENTRY(cpu_feroceon_set_pte_ext) 
	tst	r1, #L_PTE_PRESENT | L_PTE_YOUNG	@ Present and Young?

	movne	r2, #0



#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH

	eor	r3, r2, #0x0a			@ C & small page?

	tst	r3, #0x0b

	biceq	r2, r2, #4

#endif

	str	r2, [r0]			@ hardware version

	mov	r0, r0

#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH

	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry

#endif

	mcr	p15, 0, r0, c7, c10, 4		@ drain WB

#endif

	mov	pc, lr
@@ -387,12 +353,6 @@ __feroceon_setup: 
	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4

#endif





#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH

	mov	r0, #4				@ disable write-back on caches explicitly

	mcr	p15, 7, r0, c15, c0, 0

#endif



	adr	r5, feroceon_crval

	ldmia	r5, {r5, r6}

	mrc	p15, 0, r0, c1, c0		@ get control register v4