Merge "clock-alpha-pll: Enhance handoff to configure rate and outputs" (a6f82f0a) · Commits · e / devices / android_kernel_sony_msm8994

drivers/clk/qcom/clock-alpha-pll.c

+12 −2

Original line number	Diff line number	Diff line
		@@ -30,6 +30,7 @@
		#define A_REG(pll) (*pll->base + pll->offset + 0x8)
		#define VCO_REG(pll) (*pll->base + pll->offset + 0x10)
		#define ALPHA_EN_REG(pll) (*pll->base + pll->offset + 0x10)
		#define OUTPUT_REG(pll) (*pll->base + pll->offset + 0x10)

		#define PLL_BYPASSNL 0x2
		#define PLL_RESET_N 0x4
		@@ -268,18 +269,27 @@ static void update_vco_tbl(struct alpha_pll_clk *pll)
		}
		}


		static enum handoff alpha_pll_handoff(struct clk *c)
		{
		struct alpha_pll_clk *pll = to_alpha_pll_clk(c);
		struct alpha_pll_masks *masks = pll->masks;
		u64 a_val;
		u32 alpha_en, l_val;
		u32 output_en;

		update_vco_tbl(pll);

		if (!is_locked(pll))
		if (!is_locked(pll)) {
		if (c->rate && alpha_pll_set_rate(c, c->rate))
		WARN(1, "%s: Failed to configure rate\n", c->dbg_name);
		if (masks->output_mask && pll->enable_config) {
		output_en = readl_relaxed(OUTPUT_REG(pll));
		output_en &= ~masks->output_mask;
		output_en \|= pll->enable_config;
		writel_relaxed(output_en, OUTPUT_REG(pll));
		}
		return HANDOFF_DISABLED_CLK;
		}

		l_val = readl_relaxed(L_REG(pll));
		/* read u64 in two steps to satisfy alignment constraint */

+2 −0

Original line number	Diff line number	Diff line
		@@ -24,6 +24,7 @@ struct alpha_pll_masks {
		u32 vco_mask;
		u32 vco_shift;
		u32 alpha_en_mask;
		u32 output_mask;
		};

		struct alpha_pll_vco_tbl {
		@@ -42,6 +43,7 @@ struct alpha_pll_clk {
		struct alpha_pll_masks *masks;
		void const __iomem base;
		const u32 offset;
		u32 enable_config; /* bitmask of outputs to be enabled */

		struct alpha_pll_vco_tbl *vco_tbl;
		u32 num_vco;