Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a6dbba77 authored by Vitaly Bordug's avatar Vitaly Bordug Committed by Linus Torvalds
Browse files

[PATCH] ppc32: Support for 82xx PQII on-chip PCI bridge 



This patch adds on-chip PCI bridge support for the PQ2 family.  The
incomplete existent code is updated with interrupt handling stuff and
board-specific bits for 8272ADS and PQ2FADS; the related files were renamed
(from m8260_pci to m82xx_pci) to be of more generic fashion.  This is
tested with 8266ADS and 8272ADS, should work on PQ2FADS as well.

Signed-off-by: default avatarVitaly Bordug <vbordug@ru.mvista.com>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent ed369596

arch/ppc/Kconfig

+2 −2
Original line number Diff line number Diff line
@@ -1143,12 +1143,12 @@ config PCI_QSPAN 


config PCI_8260

	bool

	depends on PCI && 8260 && !8272

	depends on PCI && 8260

	default y



config 8260_PCI9

	bool "  Enable workaround for MPC826x erratum PCI 9"

	depends on PCI_8260

	depends on PCI_8260 && !ADS8272

	default y



choice

arch/ppc/platforms/pq2ads.h

+18 −23
Original line number Diff line number Diff line
@@ -49,10 +49,10 @@ 
/* PCI interrupt controller */

#define PCI_INT_STAT_REG	0xF8200000

#define PCI_INT_MASK_REG	0xF8200004

#define PIRQA			(NR_SIU_INTS + 0)

#define PIRQB			(NR_SIU_INTS + 1)

#define PIRQC			(NR_SIU_INTS + 2)

#define PIRQD			(NR_SIU_INTS + 3)

#define PIRQA			(NR_CPM_INTS + 0)

#define PIRQB			(NR_CPM_INTS + 1)

#define PIRQC			(NR_CPM_INTS + 2)

#define PIRQD			(NR_CPM_INTS + 3)



/*

 * PCI memory map definitions for MPC8266ADS-PCI.
@@ -68,28 +68,23 @@ 
 *	0x00000000-0x1FFFFFFF	0x00000000-0x1FFFFFFF	MPC8266 local memory

 */



/* window for a PCI master to access MPC8266 memory */

#define PCI_SLV_MEM_LOCAL	0x00000000	/* Local base */

#define PCI_SLV_MEM_BUS		0x00000000	/* PCI base */

/* All the other PCI memory map definitions reside at syslib/m82xx_pci.h

   Here we should redefine what is unique for this board */

#define M82xx_PCI_SLAVE_MEM_LOCAL	0x00000000	/* Local base */

#define M82xx_PCI_SLAVE_MEM_BUS		0x00000000	/* PCI base */

#define M82xx_PCI_SLAVE_MEM_SIZE	0x10000000	/* 256 Mb */



/* window for the processor to access PCI memory with prefetching */

#define PCI_MSTR_MEM_LOCAL	0x80000000	/* Local base */

#define PCI_MSTR_MEM_BUS	0x80000000	/* PCI base   */

#define PCI_MSTR_MEM_SIZE	0x20000000	/* 512MB */

#define M82xx_PCI_SLAVE_SEC_WND_SIZE	~(0x40000000 - 1U)	/* 2 x 512Mb  */

#define M82xx_PCI_SLAVE_SEC_WND_BASE	0x80000000		/* PCI Memory base */



/* window for the processor to access PCI memory without prefetching */

#define PCI_MSTR_MEMIO_LOCAL	0xA0000000	/* Local base */

#define PCI_MSTR_MEMIO_BUS	0xA0000000	/* PCI base   */

#define PCI_MSTR_MEMIO_SIZE	0x20000000	/* 512MB */

#if defined(CONFIG_ADS8272)

#define PCI_INT_TO_SIU 	SIU_INT_IRQ2

#elif defined(CONFIG_PQ2FADS)

#define PCI_INT_TO_SIU 	SIU_INT_IRQ6

#else

#warning PCI Bridge will be without interrupts support

#endif



/* window for the processor to access PCI I/O */

#define PCI_MSTR_IO_LOCAL	0xF4000000	/* Local base */

#define PCI_MSTR_IO_BUS         0x00000000	/* PCI base   */

#define PCI_MSTR_IO_SIZE        0x04000000	/* 64MB */



#define _IO_BASE		PCI_MSTR_IO_LOCAL

#define _ISA_MEM_BASE		PCI_MSTR_MEMIO_LOCAL

#define PCI_DRAM_OFFSET		PCI_SLV_MEM_BUS

#endif /* CONFIG_PCI */



#endif /* __MACH_ADS8260_DEFS */

arch/ppc/syslib/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -81,7 +81,7 @@ obj-$(CONFIG_SBC82xx) += todc_time.o 
obj-$(CONFIG_SPRUCE)		+= cpc700_pic.o indirect_pci.o pci_auto.o \

				   todc_time.o

obj-$(CONFIG_8260)		+= m8260_setup.o

obj-$(CONFIG_PCI_8260)		+= m8260_pci.o indirect_pci.o

obj-$(CONFIG_PCI_8260)		+= m82xx_pci.o indirect_pci.o pci_auto.o

obj-$(CONFIG_8260_PCI9)		+= m8260_pci_erratum9.o

obj-$(CONFIG_CPM2)		+= cpm2_common.o cpm2_pic.o

ifeq ($(CONFIG_PPC_GEN550),y)

arch/ppc/syslib/m8260_pci.c

deleted100644 → 0
+0 −193
Original line number Diff line number Diff line 
/*

 * (C) Copyright 2003

 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.

 *

 * (C) Copyright 2004 Red Hat, Inc.

 *

 * See file CREDITS for list of people who contributed to this

 * project.

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License as

 * published by the Free Software Foundation; either version 2 of

 * the License, or (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,

 * MA 02111-1307 USA

 */



#include <linux/kernel.h>

#include <linux/init.h>

#include <linux/pci.h>

#include <linux/slab.h>

#include <linux/delay.h>



#include <asm/byteorder.h>

#include <asm/io.h>

#include <asm/irq.h>

#include <asm/uaccess.h>

#include <asm/machdep.h>

#include <asm/pci-bridge.h>

#include <asm/immap_cpm2.h>

#include <asm/mpc8260.h>



#include "m8260_pci.h"





/* PCI bus configuration registers.

 */



static void __init m8260_setup_pci(struct pci_controller *hose)

{

	volatile cpm2_map_t *immap = cpm2_immr;

	unsigned long pocmr;

	u16 tempShort;



#ifndef CONFIG_ATC 	/* already done in U-Boot */

	/* 

	 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]), 

	 * and local bus for PCI (SIUMCR [LBPC]).

	 */

	immap->im_siu_conf.siu_82xx.sc_siumcr = 0x00640000;

#endif



	/* Make PCI lowest priority */

	/* Each 4 bits is a device bus request  and the MS 4bits 

	   is highest priority */

	/* Bus               4bit value 

	   ---               ----------

	   CPM high          0b0000

	   CPM middle        0b0001

	   CPM low           0b0010

	   PCI reguest       0b0011

	   Reserved          0b0100

	   Reserved          0b0101

	   Internal Core     0b0110

	   External Master 1 0b0111

	   External Master 2 0b1000

	   External Master 3 0b1001

	   The rest are reserved */

	immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x61207893;



	/* Park bus on core while modifying PCI Bus accesses */

	immap->im_siu_conf.siu_82xx.sc_ppc_acr = 0x6;



	/* 

	 * Set up master window that allows the CPU to access PCI space. This 

	 * window is set up using the first SIU PCIBR registers.

	 */

	immap->im_memctl.memc_pcimsk0 = MPC826x_PCI_MASK;

	immap->im_memctl.memc_pcibr0 =	MPC826x_PCI_BASE | PCIBR_ENABLE;



	/* Disable machine check on no response or target abort */

	immap->im_pci.pci_emr = cpu_to_le32(0x1fe7);

	/* Release PCI RST (by default the PCI RST signal is held low)  */

	immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN);



	/* give it some time */

	mdelay(1);



	/* 

	 * Set up master window that allows the CPU to access PCI Memory (prefetch) 

	 * space. This window is set up using the first set of Outbound ATU registers.

	 */

	immap->im_pci.pci_potar0 = cpu_to_le32(MPC826x_PCI_LOWER_MEM >> 12);

	immap->im_pci.pci_pobar0 = cpu_to_le32((MPC826x_PCI_LOWER_MEM - MPC826x_PCI_MEM_OFFSET) >> 12);

	pocmr = ((MPC826x_PCI_UPPER_MEM - MPC826x_PCI_LOWER_MEM) >> 12) ^ 0xfffff;

	immap->im_pci.pci_pocmr0 = cpu_to_le32(pocmr | POCMR_ENABLE | POCMR_PREFETCH_EN);



	/* 

	 * Set up master window that allows the CPU to access PCI Memory (non-prefetch) 

	 * space. This window is set up using the second set of Outbound ATU registers.

	 */

	immap->im_pci.pci_potar1 = cpu_to_le32(MPC826x_PCI_LOWER_MMIO >> 12);

	immap->im_pci.pci_pobar1 = cpu_to_le32((MPC826x_PCI_LOWER_MMIO - MPC826x_PCI_MMIO_OFFSET) >> 12);

	pocmr = ((MPC826x_PCI_UPPER_MMIO - MPC826x_PCI_LOWER_MMIO) >> 12) ^ 0xfffff;

	immap->im_pci.pci_pocmr1 = cpu_to_le32(pocmr | POCMR_ENABLE);



	/* 

	 * Set up master window that allows the CPU to access PCI IO space. This window

	 * is set up using the third set of Outbound ATU registers.

	 */

	immap->im_pci.pci_potar2 = cpu_to_le32(MPC826x_PCI_IO_BASE >> 12);

	immap->im_pci.pci_pobar2 = cpu_to_le32(MPC826x_PCI_LOWER_IO >> 12);

	pocmr = ((MPC826x_PCI_UPPER_IO - MPC826x_PCI_LOWER_IO) >> 12) ^ 0xfffff;

	immap->im_pci.pci_pocmr2 = cpu_to_le32(pocmr | POCMR_ENABLE | POCMR_PCI_IO);



	/* 

	 * Set up slave window that allows PCI masters to access MPC826x local memory. 

	 * This window is set up using the first set of Inbound ATU registers

	 */



	immap->im_pci.pci_pitar0 = cpu_to_le32(MPC826x_PCI_SLAVE_MEM_LOCAL >> 12);

	immap->im_pci.pci_pibar0 = cpu_to_le32(MPC826x_PCI_SLAVE_MEM_BUS >> 12);

	pocmr = ((MPC826x_PCI_SLAVE_MEM_SIZE-1) >> 12) ^ 0xfffff;

	immap->im_pci.pci_picmr0 = cpu_to_le32(pocmr | PICMR_ENABLE | PICMR_PREFETCH_EN);



	/* See above for description - puts PCI request as highest priority */

	immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x03124567;



	/* Park the bus on the PCI */

	immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;



	/* Host mode - specify the bridge as a host-PCI bridge */

	early_write_config_word(hose, 0, 0, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_HOST);



	/* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */

	early_read_config_word(hose, 0, 0, PCI_COMMAND, &tempShort);

	early_write_config_word(hose, 0, 0, PCI_COMMAND,

				tempShort | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);

}



void __init m8260_find_bridges(void)

{

	extern int pci_assign_all_busses;

	struct pci_controller * hose;



	pci_assign_all_busses = 1;



	hose = pcibios_alloc_controller();



	if (!hose)

		return;



	ppc_md.pci_swizzle = common_swizzle;



	hose->first_busno = 0;

	hose->bus_offset = 0;

	hose->last_busno = 0xff;



	setup_m8260_indirect_pci(hose, 

				 (unsigned long)&cpm2_immr->im_pci.pci_cfg_addr,

				 (unsigned long)&cpm2_immr->im_pci.pci_cfg_data);



	m8260_setup_pci(hose);

        hose->pci_mem_offset = MPC826x_PCI_MEM_OFFSET;



        hose->io_base_virt = ioremap(MPC826x_PCI_IO_BASE,

                                        MPC826x_PCI_IO_SIZE);

        isa_io_base = (unsigned long) hose->io_base_virt;

 

        /* setup resources */

        pci_init_resource(&hose->mem_resources[0],

			  MPC826x_PCI_LOWER_MEM,

			  MPC826x_PCI_UPPER_MEM,

			  IORESOURCE_MEM|IORESOURCE_PREFETCH, "PCI prefetchable memory");



        pci_init_resource(&hose->mem_resources[1],

			  MPC826x_PCI_LOWER_MMIO,

			  MPC826x_PCI_UPPER_MMIO,

			  IORESOURCE_MEM, "PCI memory");



        pci_init_resource(&hose->io_resource,

			  MPC826x_PCI_LOWER_IO,

			  MPC826x_PCI_UPPER_IO,

			  IORESOURCE_IO, "PCI I/O");

}

arch/ppc/syslib/m8260_pci_erratum9.c

+5 −5
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ 
#include <asm/immap_cpm2.h>

#include <asm/cpm2.h>



#include "m8260_pci.h"

#include "m82xx_pci.h"



#ifdef CONFIG_8260_PCI9

/*#include <asm/mpc8260_pci9.h>*/ /* included in asm/io.h */
@@ -248,11 +248,11 @@ EXPORT_SYMBOL(idma_pci9_read_le); 


static inline int is_pci_mem(unsigned long addr)

{

	if (addr >= MPC826x_PCI_LOWER_MMIO &&

	    addr <= MPC826x_PCI_UPPER_MMIO)

	if (addr >= M82xx_PCI_LOWER_MMIO &&

		addr <= M82xx_PCI_UPPER_MMIO)

		return 1;

	if (addr >= MPC826x_PCI_LOWER_MEM &&

	    addr <= MPC826x_PCI_UPPER_MEM)

	if (addr >= M82xx_PCI_LOWER_MEM &&

		addr <= M82xx_PCI_UPPER_MEM)

		return 1;

	return 0;

}