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Commit a4c9d034 authored by Mohan Pallaka's avatar Mohan Pallaka
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platform: msm: fix s3 source macros 



PON stage 3 source macros are wrongly ordered. Fix the
S3 source macros with proper values.

Change-Id: If68d7405d9db107a4d2aceb152589da2e34fc73b
Signed-off-by: default avatarMohan Pallaka <mpallaka@codeaurora.org>
parent 5698cb80

drivers/platform/msm/qpnp-power-on.c

+5 −2
Original line number Diff line number Diff line
@@ -90,8 +90,8 @@ 


#define QPNP_PON_S3_SRC_KPDPWR			0

#define QPNP_PON_S3_SRC_RESIN			1

#define QPNP_PON_S3_SRC_KPDPWR_OR_RESIN		2

#define QPNP_PON_S3_SRC_KPDPWR_AND_RESIN	3

#define QPNP_PON_S3_SRC_KPDPWR_AND_RESIN	2

#define QPNP_PON_S3_SRC_KPDPWR_OR_RESIN		3

#define QPNP_PON_S3_SRC_MASK			0x3



/* Ranges */
@@ -1382,6 +1382,9 @@ static int qpnp_pon_probe(struct spmi_device *spmi) 
	else /* default combination */

		s3_src_reg = QPNP_PON_S3_SRC_KPDPWR_AND_RESIN;



	/* S3 source is a write once register. If the register has

	 * been configured by bootloader then this operation will

	 * not be effective. */

	rc = qpnp_pon_masked_write(pon, QPNP_PON_S3_SRC(pon->base),

			QPNP_PON_S3_SRC_MASK, s3_src_reg);

	if (rc) {