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Commit a1f210a9 authored by Jordan Crouse's avatar Jordan Crouse
Browse files

msm: kgsl: Add A4XX coresight debug registers 



Add the list of trace bus (coresight) debug registers to enable
coresight support for the A4XX GPU family.

CRs-fixed: 535111
Change-Id: Ic0dedbadd318695d430b3625ae53fa895c1a727f
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: default avatarRajeev Kulkarni <krajeev@codeaurora.org>
parent 3392f4d9

drivers/gpu/msm/a4xx_reg.h

+42 −0
Original line number Diff line number Diff line
@@ -46,6 +46,48 @@ enum a4xx_rb_perfctr_rb_sel { 
#define A4XX_RBBM_STATUS		0x191

#define A4XX_RBBM_INT_CLEAR_CMD		0x36

#define A4XX_RBBM_INT_0_MASK		0x37

#define A4XX_RBBM_EXT_TRACE_BUS_CTL	0x49

#define A4XX_RBBM_CFG_DEBBUS_SEL_A          0x4a

#define A4XX_RBBM_CFG_DEBBUS_SEL_B          0x4b

#define A4XX_RBBM_CFG_DEBBUS_SEL_C          0x4c

#define A4XX_RBBM_CFG_DEBBUS_SEL_D          0x4d

#define A4XX_RBBM_CFG_DEBBUS_CTLT           0x4e

#define A4XX_RBBM_CFG_DEBBUS_CTLM           0x4f

#define A4XX_RBBM_CFG_DEBBUS_OPL            0x50

#define A4XX_RBBM_CFG_DEBBUS_OPE            0x51

#define A4XX_RBBM_CFG_DEBBUS_IVTL_0         0x52

#define A4XX_RBBM_CFG_DEBBUS_IVTL_1         0x53

#define A4XX_RBBM_CFG_DEBBUS_IVTL_2         0x54

#define A4XX_RBBM_CFG_DEBBUS_IVTL_3         0x55

#define A4XX_RBBM_CFG_DEBBUS_MASKL_0        0x56

#define A4XX_RBBM_CFG_DEBBUS_MASKL_1        0x57

#define A4XX_RBBM_CFG_DEBBUS_MASKL_2        0x58

#define A4XX_RBBM_CFG_DEBBUS_MASKL_3        0x59

#define A4XX_RBBM_CFG_DEBBUS_BYTEL_0        0x5a

#define A4XX_RBBM_CFG_DEBBUS_BYTEL_1        0x5b

#define A4XX_RBBM_CFG_DEBBUS_IVTE_0         0x5c

#define A4XX_RBBM_CFG_DEBBUS_IVTE_1         0x5d

#define A4XX_RBBM_CFG_DEBBUS_IVTE_2         0x5e

#define A4XX_RBBM_CFG_DEBBUS_IVTE_3         0x5f

#define A4XX_RBBM_CFG_DEBBUS_MASKE_0        0x60

#define A4XX_RBBM_CFG_DEBBUS_MASKE_1        0x61

#define A4XX_RBBM_CFG_DEBBUS_MASKE_2        0x62

#define A4XX_RBBM_CFG_DEBBUS_MASKE_3        0x63

#define A4XX_RBBM_CFG_DEBBUS_NIBBLEE        0x64

#define A4XX_RBBM_CFG_DEBBUS_PTRC0          0x65

#define A4XX_RBBM_CFG_DEBBUS_PTRC1          0x66

#define A4XX_RBBM_CFG_DEBBUS_LOADREG        0x67

#define A4XX_RBBM_CFG_DEBBUS_IDX            0x93

#define A4XX_RBBM_CFG_DEBBUS_CLRC           0x94

#define A4XX_RBBM_CFG_DEBBUS_LOADIVT        0x95

#define A4XX_RBBM_CFG_DEBBUS_TRACE_BUF0        0x1a9

#define A4XX_RBBM_CFG_DEBBUS_TRACE_BUF1        0x1aa

#define A4XX_RBBM_CFG_DEBBUS_TRACE_BUF2        0x1ab

#define A4XX_RBBM_CFG_DEBBUS_TRACE_BUF3        0x1ac

#define A4XX_RBBM_CFG_DEBBUS_TRACE_BUF4        0x1ad

#define A4XX_RBBM_CFG_DEBBUS_MISR0	0x1ae

#define A4XX_RBBM_CFG_DEBBUS_MISR1	0x1af

#define A4XX_RBBM_CFG_COUNTER0		0x1a2

#define A4XX_RBBM_INT_0_STATUS		0x17d

#define A4XX_RBBM_PERFCTR_CTL		0x170

#define A4XX_RBBM_PERFCTR_LOAD_CMD0	0x171

drivers/gpu/msm/adreno_a4xx.c

+127 −0
Original line number Diff line number Diff line
@@ -787,6 +787,132 @@ static const struct adreno_invalid_countables 
	ADRENO_PERFCOUNTER_INVALID_COUNTABLE(uche, UCHE),

};



static struct adreno_coresight_register a4xx_coresight_registers[] = {

	{ A4XX_RBBM_CFG_DEBBUS_CTLT },

	{ A4XX_RBBM_CFG_DEBBUS_SEL_A },

	{ A4XX_RBBM_CFG_DEBBUS_SEL_B },

	{ A4XX_RBBM_CFG_DEBBUS_SEL_C },

	{ A4XX_RBBM_CFG_DEBBUS_SEL_D },

	{ A4XX_RBBM_CFG_DEBBUS_OPL },

	{ A4XX_RBBM_CFG_DEBBUS_OPE },

	{ A4XX_RBBM_CFG_DEBBUS_IVTL_0 },

	{ A4XX_RBBM_CFG_DEBBUS_IVTL_1 },

	{ A4XX_RBBM_CFG_DEBBUS_IVTL_2 },

	{ A4XX_RBBM_CFG_DEBBUS_IVTL_3 },

	{ A4XX_RBBM_CFG_DEBBUS_MASKL_0 },

	{ A4XX_RBBM_CFG_DEBBUS_MASKL_1 },

	{ A4XX_RBBM_CFG_DEBBUS_MASKL_2 },

	{ A4XX_RBBM_CFG_DEBBUS_MASKL_3 },

	{ A4XX_RBBM_CFG_DEBBUS_BYTEL_0 },

	{ A4XX_RBBM_CFG_DEBBUS_BYTEL_1 },

	{ A4XX_RBBM_CFG_DEBBUS_IVTE_0 },

	{ A4XX_RBBM_CFG_DEBBUS_IVTE_1 },

	{ A4XX_RBBM_CFG_DEBBUS_IVTE_2 },

	{ A4XX_RBBM_CFG_DEBBUS_IVTE_3 },

	{ A4XX_RBBM_CFG_DEBBUS_MASKE_0 },

	{ A4XX_RBBM_CFG_DEBBUS_MASKE_1 },

	{ A4XX_RBBM_CFG_DEBBUS_MASKE_2 },

	{ A4XX_RBBM_CFG_DEBBUS_MASKE_3 },

	{ A4XX_RBBM_CFG_DEBBUS_NIBBLEE },

	{ A4XX_RBBM_CFG_DEBBUS_PTRC0 },

	{ A4XX_RBBM_CFG_DEBBUS_PTRC1 },

	{ A4XX_RBBM_CFG_DEBBUS_CLRC },

	{ A4XX_RBBM_CFG_DEBBUS_LOADIVT },

	{ A4XX_RBBM_CFG_DEBBUS_IDX },

	{ A4XX_RBBM_CFG_DEBBUS_LOADREG },

	{ A4XX_RBBM_EXT_TRACE_BUS_CTL },

	{ A4XX_RBBM_CFG_DEBBUS_CTLM },

};



static ADRENO_CORESIGHT_ATTR(cfg_debbus_ctrlt, &a4xx_coresight_registers[0]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_sela, &a4xx_coresight_registers[1]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_selb, &a4xx_coresight_registers[2]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_selc, &a4xx_coresight_registers[3]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_seld, &a4xx_coresight_registers[4]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_opl, &a4xx_coresight_registers[5]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_ope, &a4xx_coresight_registers[6]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_ivtl0, &a4xx_coresight_registers[7]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_ivtl1, &a4xx_coresight_registers[8]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_ivtl2, &a4xx_coresight_registers[9]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_ivtl3, &a4xx_coresight_registers[10]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_maskl0, &a4xx_coresight_registers[11]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_maskl1, &a4xx_coresight_registers[12]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_maskl2, &a4xx_coresight_registers[13]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_maskl3, &a4xx_coresight_registers[14]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_bytel0, &a4xx_coresight_registers[15]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_bytel1, &a4xx_coresight_registers[16]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_ivte0, &a4xx_coresight_registers[17]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_ivte1, &a4xx_coresight_registers[18]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_ivte2, &a4xx_coresight_registers[19]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_ivte3, &a4xx_coresight_registers[20]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_maske0, &a4xx_coresight_registers[21]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_maske1, &a4xx_coresight_registers[22]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_maske2, &a4xx_coresight_registers[23]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_maske3, &a4xx_coresight_registers[24]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_nibblee, &a4xx_coresight_registers[25]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_ptrc0, &a4xx_coresight_registers[26]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_ptrc1, &a4xx_coresight_registers[27]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_clrc, &a4xx_coresight_registers[28]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_loadivt, &a4xx_coresight_registers[29]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_idx, &a4xx_coresight_registers[30]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_loadreg, &a4xx_coresight_registers[31]);

static ADRENO_CORESIGHT_ATTR(ext_tracebus_ctl, &a4xx_coresight_registers[32]);

static ADRENO_CORESIGHT_ATTR(cfg_debbus_ctrlm, &a4xx_coresight_registers[33]);





static struct attribute *a4xx_coresight_attrs[] = {

	&coresight_attr_cfg_debbus_ctrlt.attr.attr,

	&coresight_attr_cfg_debbus_sela.attr.attr,

	&coresight_attr_cfg_debbus_selb.attr.attr,

	&coresight_attr_cfg_debbus_selc.attr.attr,

	&coresight_attr_cfg_debbus_seld.attr.attr,

	&coresight_attr_cfg_debbus_opl.attr.attr,

	&coresight_attr_cfg_debbus_ope.attr.attr,

	&coresight_attr_cfg_debbus_ivtl0.attr.attr,

	&coresight_attr_cfg_debbus_ivtl1.attr.attr,

	&coresight_attr_cfg_debbus_ivtl2.attr.attr,

	&coresight_attr_cfg_debbus_ivtl3.attr.attr,

	&coresight_attr_cfg_debbus_maskl0.attr.attr,

	&coresight_attr_cfg_debbus_maskl1.attr.attr,

	&coresight_attr_cfg_debbus_maskl2.attr.attr,

	&coresight_attr_cfg_debbus_maskl3.attr.attr,

	&coresight_attr_cfg_debbus_bytel0.attr.attr,

	&coresight_attr_cfg_debbus_bytel1.attr.attr,

	&coresight_attr_cfg_debbus_ivte0.attr.attr,

	&coresight_attr_cfg_debbus_ivte1.attr.attr,

	&coresight_attr_cfg_debbus_ivte2.attr.attr,

	&coresight_attr_cfg_debbus_ivte3.attr.attr,

	&coresight_attr_cfg_debbus_maske0.attr.attr,

	&coresight_attr_cfg_debbus_maske1.attr.attr,

	&coresight_attr_cfg_debbus_maske2.attr.attr,

	&coresight_attr_cfg_debbus_maske3.attr.attr,

	&coresight_attr_cfg_debbus_nibblee.attr.attr,

	&coresight_attr_cfg_debbus_ptrc0.attr.attr,

	&coresight_attr_cfg_debbus_ptrc1.attr.attr,

	&coresight_attr_cfg_debbus_clrc.attr.attr,

	&coresight_attr_cfg_debbus_loadivt.attr.attr,

	&coresight_attr_cfg_debbus_idx.attr.attr,

	&coresight_attr_cfg_debbus_loadreg.attr.attr,

	&coresight_attr_ext_tracebus_ctl.attr.attr,

	&coresight_attr_cfg_debbus_ctrlm.attr.attr,

	NULL,

};



static const struct attribute_group a4xx_coresight_group = {

	.attrs = a4xx_coresight_attrs,

};



static const struct attribute_group *a4xx_coresight_groups[] = {

	&a4xx_coresight_group,

	NULL,

};



static struct adreno_coresight a4xx_coresight = {

	.registers = a4xx_coresight_registers,

	.count = ARRAY_SIZE(a4xx_coresight_registers),

	.groups = a4xx_coresight_groups,

};



struct adreno_gpudev adreno_a4xx_gpudev = {

	.reg_offsets = &a4xx_reg_offsets,

	.perfcounters = &a4xx_perfcounters,
@@ -796,6 +922,7 @@ struct adreno_gpudev adreno_a4xx_gpudev = { 
	.irq_handler = a3xx_irq_handler,

	.irq_pending = a3xx_irq_pending,

	.busy_cycles = a3xx_busy_cycles,

	.coresight = &a4xx_coresight,

	.start = a4xx_start,

	.perfcounter_enable = a3xx_perfcounter_enable,

	.perfcounter_read = a3xx_perfcounter_read,