Loading arch/arm/boot/dts/qcom/msm8916.dtsi +4 −4 Original line number Diff line number Diff line Loading @@ -47,7 +47,7 @@ #address-cells = <1>; #size-cells = <0>; cpu@0 { CPU0: cpu@0 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0>; Loading @@ -61,7 +61,7 @@ }; }; cpu@1 { CPU1: cpu@1 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x1>; Loading @@ -70,7 +70,7 @@ next-level-cache = <&L2_0>; }; cpu@2 { CPU2: cpu@2 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x2>; Loading @@ -79,7 +79,7 @@ next-level-cache = <&L2_0>; }; cpu@3 { CPU3: cpu@3 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x3>; Loading Loading
arch/arm/boot/dts/qcom/msm8916.dtsi +4 −4 Original line number Diff line number Diff line Loading @@ -47,7 +47,7 @@ #address-cells = <1>; #size-cells = <0>; cpu@0 { CPU0: cpu@0 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0>; Loading @@ -61,7 +61,7 @@ }; }; cpu@1 { CPU1: cpu@1 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x1>; Loading @@ -70,7 +70,7 @@ next-level-cache = <&L2_0>; }; cpu@2 { CPU2: cpu@2 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x2>; Loading @@ -79,7 +79,7 @@ next-level-cache = <&L2_0>; }; cpu@3 { CPU3: cpu@3 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x3>; Loading