Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

This project is archived. Its data is read-only.

Commit a164ffe5 authored May 21, 2014 by Mayank Rana

usb: ci13xxx_msm_hsic: Set USB HSIC Core related clk rate before using



It is must to set peripheral's clock rate before using it even it is
having single clock frequency to use. Hence set USB HSIC core related
clocks' rate before using and enabling it.

Change-Id: Iec32fdd774a32c13917176255163dd02383c1e55
Signed-off-by: Mayank Rana <mrana@codeaurora.org>

parent f8452180

drivers/usb/gadget/ci13xxx_msm_hsic.c

+27 −6

Original line number	Diff line number	Diff line
		@@ -238,37 +238,57 @@ static int msm_hsic_enable_clocks(struct platform_device *pdev,
		if (IS_ERR(mhsic->iface_clk)) {
		dev_err(mhsic->dev, "failed to get iface_clk\n");
		ret = PTR_ERR(mhsic->iface_clk);
		goto put_iface_clk;
		goto error_enable_clocks;
		}

		mhsic->core_clk = clk_get(&pdev->dev, "core_clk");
		if (IS_ERR(mhsic->core_clk)) {
		dev_err(mhsic->dev, "failed to get core_clk\n");
		ret = PTR_ERR(mhsic->core_clk);
		goto put_core_clk;
		goto put_iface_clk;
		}

		ret = clk_set_rate(mhsic->core_clk,
		clk_round_rate(mhsic->core_clk, LONG_MAX));
		if (ret)
		dev_err(mhsic->dev, "failed to set core_clk rate\n");

		mhsic->phy_clk = clk_get(&pdev->dev, "phy_clk");
		if (IS_ERR(mhsic->phy_clk)) {
		dev_err(mhsic->dev, "failed to get phy_clk\n");
		ret = PTR_ERR(mhsic->phy_clk);
		goto put_phy_clk;
		goto put_core_clk;
		}

		ret = clk_set_rate(mhsic->phy_clk,
		clk_round_rate(mhsic->phy_clk, LONG_MAX));
		if (ret)
		dev_err(mhsic->dev, "failed to set phy_clk rate\n");

		mhsic->alt_core_clk = clk_get(&pdev->dev, "alt_core_clk");
		if (IS_ERR(mhsic->alt_core_clk)) {
		dev_err(mhsic->dev, "failed to get alt_core_clk\n");
		ret = PTR_ERR(mhsic->alt_core_clk);
		goto put_alt_core_clk;
		goto put_phy_clk;
		}

		ret = clk_set_rate(mhsic->alt_core_clk,
		clk_round_rate(mhsic->alt_core_clk, LONG_MAX));
		if (ret)
		dev_err(mhsic->dev, "failed to set alt_core_clk rate\n");

		mhsic->cal_clk = clk_get(&pdev->dev, "cal_clk");
		if (IS_ERR(mhsic->cal_clk)) {
		dev_err(mhsic->dev, "failed to get cal_clk\n");
		ret = PTR_ERR(mhsic->cal_clk);
		goto put_cal_clk;
		goto put_alt_core_clk;
		}

		ret = clk_set_rate(mhsic->cal_clk,
		clk_round_rate(mhsic->cal_clk, LONG_MAX));
		if (ret)
		dev_err(mhsic->dev, "failed to set cal_clk rate\n");

		clk_prepare_enable(mhsic->iface_clk);
		clk_prepare_enable(mhsic->core_clk);
		clk_prepare_enable(mhsic->phy_clk);
		@@ -283,7 +303,7 @@ put_clocks:
		clk_disable_unprepare(mhsic->phy_clk);
		clk_disable_unprepare(mhsic->alt_core_clk);
		clk_disable_unprepare(mhsic->cal_clk);
		put_cal_clk:

		clk_put(mhsic->cal_clk);
		put_alt_core_clk:
		clk_put(mhsic->alt_core_clk);
		@@ -293,6 +313,7 @@ put_core_clk:
		clk_put(mhsic->core_clk);
		put_iface_clk:
		clk_put(mhsic->iface_clk);
		error_enable_clocks:

		return ret;
		}