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Commit a03bd9b8 authored by David Keitel's avatar David Keitel
Browse files

power: qpnp-charger: wake up upon fast charge after resuming 



When state of charge based charge resume happens there is
a delay between enabling charging again in hardware and
the fast charge state being reached. During this time
the system may have gone to suspend and the necessary
information is not conveyed to userspace.

Fix this by enabling the fast charge interrupt as a
wakeup interrupt when the SOC based resume event occurs.
Disable it when within the fast charge interrupt handler.

Change-Id: I286b1c12dbf057de974afb4084d92c157f08eee4
CRs-Fixed: 606012
Signed-off-by: default avatarDavid Keitel <dkeitel@codeaurora.org>
parent 5471a014

drivers/power/qpnp-charger.c

+30 −9
Original line number Diff line number Diff line
@@ -219,6 +219,7 @@ 
struct qpnp_chg_irq {

	int		irq;

	unsigned long		disabled;

	unsigned long		wake_enable;

};



struct qpnp_chg_regulator {
@@ -534,6 +535,24 @@ qpnp_chg_disable_irq(struct qpnp_chg_irq *irq) 
	}

}



static void

qpnp_chg_irq_wake_enable(struct qpnp_chg_irq *irq)

{

	if (!__test_and_set_bit(0, &irq->wake_enable)) {

		pr_debug("number = %d\n", irq->irq);

		enable_irq_wake(irq->irq);

	}

}



static void

qpnp_chg_irq_wake_disable(struct qpnp_chg_irq *irq)

{

	if (__test_and_clear_bit(0, &irq->wake_enable)) {

		pr_debug("number = %d\n", irq->irq);

		disable_irq_wake(irq->irq);

	}

}



#define USB_OTG_EN_BIT	BIT(0)

static int

qpnp_chg_is_otg_en_set(struct qpnp_chg_chip *chip)
@@ -1733,6 +1752,7 @@ qpnp_chg_chgr_chg_fastchg_irq_handler(int irq, void *_chip) 
	struct qpnp_chg_chip *chip = _chip;

	bool fastchg_on = false;



	qpnp_chg_irq_wake_disable(&chip->chg_fastchg);

	fastchg_on = qpnp_chg_is_fastchg_on(chip);



	pr_debug("FAST_CHG IRQ triggered, fastchg_on: %d\n", fastchg_on);
@@ -2208,6 +2228,7 @@ get_prop_capacity(struct qpnp_chg_chip *chip) 
				&& soc <= chip->soc_resume_limit) {

			pr_debug("resuming charging at %d%% soc\n", soc);

			chip->resuming_charging = true;

			qpnp_chg_irq_wake_enable(&chip->chg_fastchg);

			qpnp_chg_set_appropriate_vbatdet(chip);

			qpnp_chg_charge_en(chip, !chip->charging_disabled);

		}
@@ -3909,10 +3930,10 @@ qpnp_chg_request_irqs(struct qpnp_chg_chip *chip) 
				return rc;

			}



			enable_irq_wake(chip->chg_trklchg.irq);

			enable_irq_wake(chip->chg_failed.irq);

			qpnp_chg_irq_wake_enable(&chip->chg_trklchg);

			qpnp_chg_irq_wake_enable(&chip->chg_failed);

			qpnp_chg_disable_irq(&chip->chg_vbatdet_lo);

			enable_irq_wake(chip->chg_vbatdet_lo.irq);

			qpnp_chg_irq_wake_enable(&chip->chg_vbatdet_lo);



			break;

		case SMBB_BAT_IF_SUBTYPE:
@@ -3935,7 +3956,7 @@ qpnp_chg_request_irqs(struct qpnp_chg_chip *chip) 
				return rc;

			}



			enable_irq_wake(chip->batt_pres.irq);

			qpnp_chg_irq_wake_enable(&chip->batt_pres);



			chip->batt_temp_ok.irq = spmi_get_irq_byname(spmi,

						spmi_resource, "bat-temp-ok");
@@ -3954,7 +3975,7 @@ qpnp_chg_request_irqs(struct qpnp_chg_chip *chip) 
			}

			qpnp_chg_bat_if_batt_temp_irq_handler(0, chip);



			enable_irq_wake(chip->batt_temp_ok.irq);

			qpnp_chg_irq_wake_enable(&chip->batt_temp_ok);



			break;

		case SMBB_BUCK_SUBTYPE:
@@ -4036,11 +4057,11 @@ qpnp_chg_request_irqs(struct qpnp_chg_chip *chip) 
					return rc;

				}



				enable_irq_wake(chip->usb_ocp.irq);

				qpnp_chg_irq_wake_enable(&chip->usb_ocp);

			}



			enable_irq_wake(chip->usbin_valid.irq);

			enable_irq_wake(chip->chg_gone.irq);

			qpnp_chg_irq_wake_enable(&chip->usbin_valid);

			qpnp_chg_irq_wake_enable(&chip->chg_gone);

			break;

		case SMBB_DC_CHGPTH_SUBTYPE:

			chip->dcin_valid.irq = spmi_get_irq_byname(spmi,
@@ -4059,7 +4080,7 @@ qpnp_chg_request_irqs(struct qpnp_chg_chip *chip) 
				return rc;

			}



			enable_irq_wake(chip->dcin_valid.irq);

			qpnp_chg_irq_wake_enable(&chip->dcin_valid);

			break;

		}

	}