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Commit 9e9b3f27 authored by Vikram Mulukutla's avatar Vikram Mulukutla
Browse files

qcom: clock-cpu-8994: Add support to bringup A57 clocks before probe 



smp_init runs before the clock-cpu-8994 driver has had a chance
to probe, but the A57 clocks need to be setup before smp_init runs.

To allow this, setup the A57 clocks in an early_initcall function.

Change-Id: Ib5c7f180b09120f2d7dbf63937765bec860d8ab0
Signed-off-by: default avatarVikram Mulukutla <markivx@codeaurora.org>
parent 65c7182d

drivers/clk/qcom/clock-cpu-8994.c

+69 −0
Original line number Diff line number Diff line
@@ -1031,5 +1031,74 @@ static void __exit cpu_clock_8994_exit(void) 
}

module_exit(cpu_clock_8994_exit);



#define ALIAS1_GLB_BASE_PHY 0xF900F000

#define C1_PLL_BASE_PHY 0xF9016000



/* Setup the A57 clocks before _this_ driver probes, before smp_init */

int __init cpu_clock_8994_init_a57(void)

{

	u32 regval;

	int xo_sel, lfmux_sel, safe_sel;

	struct device_node *ofnode = of_find_compatible_node(NULL, NULL,

							"qcom,cpu-clock-8994");

	if (!ofnode)

		return 0;



	/*

	 * One time configuration message. This is extremely important to know

	 * if the boot-time configuration has't hung the CPU(s).

	 */

	pr_info("clock-cpu-8994: configuring clocks for the A57 cluster\n");



	vbases[ALIAS1_GLB_BASE] = ioremap(ALIAS1_GLB_BASE_PHY, SZ_4K);

	if (!vbases[ALIAS1_GLB_BASE]) {

		WARN(1, "Unable to ioremap A57 mux base. Can't configure A57 clocks.\n");

		return -ENOMEM;

	}



	vbases[C1_PLL_BASE] = ioremap(C1_PLL_BASE_PHY, SZ_4K);

	if (!vbases[C1_PLL_BASE]) {

		WARN(1, "Unable to ioremap A57 pll base. Can't configure A57 clocks.\n");

		return -ENOMEM;

	}



	xo_sel = parent_to_src_sel(a57_lf_mux.parents, a57_lf_mux.num_parents,

				   &xo_ao.c);

	lfmux_sel = parent_to_src_sel(a57_hf_mux.parents,

					a57_hf_mux.num_parents, &a57_lf_mux.c);

	safe_sel = parent_to_src_sel(a57_lf_mux.parents, a57_lf_mux.num_parents,

					&a57_safe_clk.c);



	__cpu_mux_set_sel(&a57_lf_mux, xo_sel);

	__cpu_mux_set_sel(&a57_hf_mux, lfmux_sel);



	a57_pll1.c.ops->disable(&a57_pll1.c);



	/* Set the main/aux output divider on the A57 primary PLL to 4 */

	regval = readl_relaxed(vbases[C1_PLL_BASE] + C1_PLLA_USER_CTL);

	regval &= ~BM(9, 8);

	regval |= (0x3 << 8);

	writel_relaxed(regval, vbases[C1_PLL_BASE] + C1_PLLA_USER_CTL);



	a57_pll1.c.ops->set_rate(&a57_pll1.c, 1593600000);



	/* Set the divider on the PLL1 input to the A57 LF MUX (div 2) */

	regval = readl_relaxed(vbases[ALIAS1_GLB_BASE] + MUX_OFFSET);

	regval |= BIT(6);

	writel_relaxed(regval, vbases[ALIAS1_GLB_BASE] + MUX_OFFSET);



	a57_pll1.c.ops->enable(&a57_pll1.c);



	__cpu_mux_set_sel(&a57_lf_mux, safe_sel);



	iounmap(vbases[ALIAS1_GLB_BASE]);

	iounmap(vbases[C1_PLL_BASE]);



	pr_cont("clock-cpu-8994: finished configuring A57 cluster clocks.\n");



	return 0;

}

early_initcall(cpu_clock_8994_init_a57);



MODULE_DESCRIPTION("CPU clock driver for 8994");

MODULE_LICENSE("GPL v2");