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Commit 9e3c0066 authored by Shawn Guo's avatar Shawn Guo
Browse files

ARM: dts: imx6q-arm2: add pinctrl for uart and enet



Add missing pinctrl of uart and enet for imx6q-arm2 board.

Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent 99d5f0cc
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+21 −0
Original line number Diff line number Diff line
@@ -28,8 +28,27 @@
			status = "disabled"; /* gpmi nand conflicts with SD */
		};

		aips-bus@02000000 { /* AIPS1 */
			iomuxc@020e0000 {
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_hog>;

				hog {
					pinctrl_hog: hoggrp {
						fsl,pins = <
							176  0x80000000	/* MX6Q_PAD_EIM_D25__GPIO_3_25 */
							1363 0x80000000	/* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
							1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
						>;
					};
				};
			};
		};

		aips-bus@02100000 { /* AIPS2 */
			ethernet@02188000 {
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_enet_2>;
				phy-mode = "rgmii";
				status = "okay";
			};
@@ -52,6 +71,8 @@
			};

			uart4: serial@021f0000 {
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_uart4_1>;
				status = "okay";
			};
		};
+29 −0
Original line number Diff line number Diff line
@@ -552,6 +552,26 @@
							48  0x1b0b0	/* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
						>;
					};

					pinctrl_enet_2: enetgrp-2 {
						fsl,pins = <
							890 0x1b0b0	/* MX6Q_PAD_KEY_COL1__ENET_MDIO */
							909 0x1b0b0	/* MX6Q_PAD_KEY_COL2__ENET_MDC */
							24  0x1b0b0	/* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
							30  0x1b0b0	/* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
							34  0x1b0b0	/* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
							39  0x1b0b0	/* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
							44  0x1b0b0	/* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
							56  0x1b0b0	/* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
							702 0x1b0b0	/* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
							74  0x1b0b0	/* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
							52  0x1b0b0	/* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
							61  0x1b0b0	/* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
							66  0x1b0b0	/* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
							70  0x1b0b0	/* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
							48  0x1b0b0	/* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
						>;
					};
				};

				gpmi-nand {
@@ -598,6 +618,15 @@
					};
				};

				uart4 {
					pinctrl_uart4_1: uart4grp-1 {
						fsl,pins = <
							877 0x1b0b1	/* MX6Q_PAD_KEY_COL0__UART4_TXD */
							885 0x1b0b1	/* MX6Q_PAD_KEY_ROW0__UART4_RXD */
						>;
					};
				};

				usdhc3 {
					pinctrl_usdhc3_1: usdhc3grp-1 {
						fsl,pins = <