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Commit 9d36b102 authored by Lokesh Batra's avatar Lokesh Batra Committed by Lynus Vaz
Browse files

ARM: dts: msm8916: Add clocks and clock-names properties 



The clocks required by GPU need to be specified in its device tree
file using the 'clocks' and 'clock-names' properties. This is a
replacement of the clock lookup table.

Change-Id: Ia726e0e2520d700fb31c81b6c0f93e738e2dfc35
Signed-off-by: default avatarLokesh Batra <lbatra@codeaurora.org>
parent ff2b0399

Documentation/devicetree/bindings/gpu/adreno.txt

+63 −57
Original line number Diff line number Diff line
@@ -23,6 +23,14 @@ Required properties: 
				KGSL_CLK_MEM_IFACE 0x00000010

				KGSL_CLK_AXI    0x00000020



- clocks:		List of phandle and clock specifier pairs, one pair

			for each clock input to the device.

- clock-names:		List of clock input name strings sorted in the same

			order as the clocks property.

				Current values of clock-names are:

				"src_clk", "core_clk", "iface_clk", "mem_clk", "mem_iface_clk",

				"alt_mem_iface_clk"



Bus Scaling Data:

- qcom,msm-bus,name: String property to describe the name of the 3D graphics processor.

- qcom,msm-bus,num-cases: This is the the number of Bus Scaling use cases defined in the vectors property.
@@ -85,46 +93,65 @@ Documentation/devicetree/bindings/coresight/coresight.txt 
- coresight-child-ports  List of input port numbers of the children.





Example of A330 GPU in MSM8974:

Example of A330 GPU in MSM8916:



/ {

	qcom,kgsl-3d0@fdb00000 {

&soc {

	msm_gpu: qcom,kgsl-3d0@01c00000 {

		label = "kgsl-3d0";

		compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";

		reg = <0xfdb00000 0x10000

		       0xfdb20000 0x10000>;

		reg = <0x01c00000 0x10000

		       0x01c20000 0x20000>;

		reg-names = "kgsl_3d0_reg_memory" , "kgsl_3d0_shader_memory";

		interrupts = <0 33 0>;

		interrupt-names = "kgsl_3d0_irq";

		qcom,id = <0>;



		qcom,chipid = <0x03030000>;



		/* Power Settings */

		qcom,chipid = <0x03000600>;



		qcom,initial-pwrlevel = <1>;

		qcom,idle-timeout = <83>; //<HZ/12>

		qcom,clk-map = <0x00000016>; //KGSL_CLK_CORE | KGSL_CLK_IFACE | KGSL_CLK_MEM_IFACE



		/* Idle Timeout = HZ/12 */

		qcom,idle-timeout = <8>;

		qcom,strtstp-sleepwake;



		/*

		 * Clocks = KGSL_CLK_CORE | KGSL_CLK_IFACE | KGSL_CLK_MEM |

		 * KGSL_CLK_MEM_IFACE | KGSL_CLK_ALT_MEM_IFACE

		 */

		qcom,clk-map = <0x0000005E>;

		clocks = <&clock_gcc clk_gcc_oxili_gfx3d_clk>,

			<&clock_gcc clk_gcc_oxili_ahb_clk>,

			<&clock_gcc clk_gcc_oxili_gmem_clk>,

			<&clock_gcc clk_gcc_bimc_gfx_clk>,

			<&clock_gcc clk_gcc_bimc_gpu_clk>;

		clock-names = "core_clk", "iface_clk", "mem_clk",

				"mem_iface_clk", "alt_mem_iface_clk";



		/* Bus Scale Settings */

		qcom,msm-bus,name = "grp3d";

		qcom,msm-bus,num-cases = <6>;

		qcom,msm-bus,num-paths = <2>;

		qcom,msm-bus,num-cases = <4>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<26 512 0 0>, <89 604 0 0>,

				<26 512 0 2200000>, <89 604 0 3000000>,

				<26 512 0 4000000>, <89 604 0 3000000>,

				<26 512 0 4000000>, <89 604 0 4500000>,

				<26 512 0 6400000>, <89 604 0 4500000>,

				<26 512 0 6400000>, <89 604 0 7600000>;

			<26 512 0 0>,

			<26 512 0 1600000>,

			<26 512 0 3200000>,

			<26 512 0 4264000>;



		/* GDSC oxili regulators */

		vddcx-supply = <&gdsc_oxili_cx>;

		vdd-supply = <&gdsc_oxili_gx>;



		/* IOMMU Data */

		iommu = <&kgsl>;

		iommu = <&gfx_iommu>;



		/* Trace bus */

		coresight-id = <67>;

		coresight-name = "coresight-gfx";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <5>;



		/* Power levels */

		qcom,gpu-pwrlevels {

			#address-cells = <1>;

			#size-cells = <0>;
@@ -133,53 +160,32 @@ Example of A330 GPU in MSM8974: 


			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <5000000000>;

				qcom,gpu-freq = <400000000>;

				qcom,bus-freq = <3>;

				qcom,io-fraction = <0>;

			};

		};



		qcom,dcvs-core-info {

			#address-cells = <1>;

			#size-cells = <0>;



			compatible = "qcom,dcvs-core-info";



			qcom,core-max-time-us = <100000>;

			qcom,algo-slack-time-us = <39000>;

			qcom,algo-disable-pc-threshold = <86000>;

			qcom,algo-ss-window-size = <1000000>;

			qcom,algo-ss-util-pct = <95>;

			qcom,algo-em-max-util-pct = <97>;

			qcom,algo-ss-no-corr-below-freq = <0>;



			qcom,dcvs-freq@0 {

				reg = <0>;

				qcom,freq = <0>;

				qcom,idle-energy = <0>;

				qcom,active-energy = <333932>;

				qcom,io-fraction = <33>;

			};



			qcom,dcvs-freq@1 {

			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,freq = <0>;

				qcom,idle-energy = <0>;

				qcom,active-energy = <497532>;

				qcom,gpu-freq = <310000000>;

				qcom,bus-freq = <2>;

				qcom,io-fraction = <66>;

			};



			qcom,dcvs-freq@2 {

			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,freq = <0>;

				qcom,idle-energy = <0>;

				qcom,active-energy = <707610>;

				qcom,gpu-freq = <200000000>;

				qcom,bus-freq = <1>;

				qcom,io-fraction = <100>;

			};



			qcom,dcvs-freq@3 {

			qcom,gpu-pwrlevel@3 {

				reg = <3>;

				qcom,freq = <0>;

				qcom,idle-energy = <0>;

				qcom,active-energy = <844545>;

				qcom,gpu-freq = <27000000>;

				qcom,bus-freq = <0>;

				qcom,io-fraction = <0>;

			};

		};



	};

};

arch/arm/boot/dts/qcom/msm8916-gpu.dtsi

+12 −2
Original line number Diff line number Diff line
@@ -29,8 +29,18 @@ 
		qcom,idle-timeout = <8>;

		qcom,strtstp-sleepwake;



		/* Clocks = KGSL_CLK_CORE | KGSL_CLK_IFACE */

		qcom,clk-map = <0x00000006>;

		/*

		 * Clocks = KGSL_CLK_CORE | KGSL_CLK_IFACE | KGSL_CLK_MEM |

		 * KGSL_CLK_MEM_IFACE | KGSL_CLK_ALT_MEM_IFACE

		 */

		qcom,clk-map = <0x0000005E>;

		clocks = <&clock_gcc clk_gcc_oxili_gfx3d_clk>,

			<&clock_gcc clk_gcc_oxili_ahb_clk>,

			<&clock_gcc clk_gcc_oxili_gmem_clk>,

			<&clock_gcc clk_gcc_bimc_gfx_clk>,

			<&clock_gcc clk_gcc_bimc_gpu_clk>;

		clock-names = "core_clk", "iface_clk", "mem_clk",

				"mem_iface_clk", "alt_mem_iface_clk";



		/* Bus Scale Settings */

		qcom,msm-bus,name = "grp3d";