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Commit 9c6b0502 authored by Asish Bhattacharya's avatar Asish Bhattacharya Committed by Aravind Kumar
Browse files

ASoC: msm8x16: add support to configure bit clock based on LPCM format. 



For 32bit I2S mode use Q6AFE_LPASS_IBIT_CLK_3_P072_MHZ and use exisitng
Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ for 16bit I2S.

Change-Id: I329f3b6f26d9e78ae78851bea765009d74deb4df
CRs-Fixed: 652063
Signed-off-by: default avatarAsish Bhattacharya <asishb@codeaurora.org>
parent 9946a704

sound/soc/codecs/msm8x16-wcd.c

+2 −1
Original line number Diff line number Diff line
@@ -46,7 +46,8 @@ 


#define MSM8X16_WCD_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\

			SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)

#define MSM8X16_WCD_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)

#define MSM8X16_WCD_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\

		SNDRV_PCM_FMTBIT_S24_LE)



#define NUM_DECIMATORS		2

#define NUM_INTERPOLATORS	3

sound/soc/msm/msm8x16.c

+6 −1
Original line number Diff line number Diff line
@@ -268,7 +268,12 @@ static int mi2s_clk_ctl(struct snd_pcm_substream *substream, bool enable) 
	int ret = 0;

	if (enable) {

		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {

			mi2s_rx_clk.clk_val1 = Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ;

			if (mi2s_rx_bit_format == SNDRV_PCM_FORMAT_S24_LE)

				mi2s_rx_clk.clk_val1 =

					Q6AFE_LPASS_IBIT_CLK_3_P072_MHZ;

			else

				mi2s_rx_clk.clk_val1 =

					Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ;

			ret = afe_set_lpass_clock(AFE_PORT_ID_PRIMARY_MI2S_RX,

						  &mi2s_rx_clk);

		} else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {

sound/soc/msm/qdsp6v2/msm-dai-q6-v2.c

+2 −1
Original line number Diff line number Diff line
@@ -2370,7 +2370,8 @@ static struct snd_soc_dai_driver msm_dai_q6_mi2s_dai[] = { 
			.aif_name = "PRI_MI2S_RX",

			.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |

			SNDRV_PCM_RATE_16000,

			.formats = SNDRV_PCM_FMTBIT_S16_LE,

			.formats = SNDRV_PCM_FMTBIT_S16_LE |

				SNDRV_PCM_FMTBIT_S24_LE,

			.rate_min =     8000,

			.rate_max =     48000,

		},