Loading drivers/platform/msm/qpnp-power-on.c +12 −0 Original line number Diff line number Diff line Loading @@ -66,6 +66,9 @@ #define QPNP_PON_S3_DBC_CTL(base) (base + 0x75) #define QPNP_PON_TRIGGER_EN(base) (base + 0x80) #define QPNP_PON_XVDD_RB_SPARE(base) (base + 0x8E) #define QPNP_PON_SEC_ACCESS(base) (base + 0xD0) #define QPNP_PON_SEC_UNLOCK 0xA5 #define QPNP_PON_WARM_RESET_TFT BIT(4) Loading Loading @@ -1541,6 +1544,15 @@ static int qpnp_pon_probe(struct spmi_device *spmi) /* 0 is a special value to indicate instant s3 reset */ if (s3_debounce != 0) s3_debounce = ilog2(s3_debounce); /* s3 debounce is SEC_ACCESS register */ rc = qpnp_pon_masked_write(pon, QPNP_PON_SEC_ACCESS(pon->base), 0xFF, QPNP_PON_SEC_UNLOCK); if (rc) { dev_err(&spmi->dev, "Unable to do SEC_ACCESS\n"); return rc; } rc = qpnp_pon_masked_write(pon, QPNP_PON_S3_DBC_CTL(pon->base), QPNP_PON_S3_DBC_DELAY_MASK, s3_debounce); if (rc) { Loading Loading
drivers/platform/msm/qpnp-power-on.c +12 −0 Original line number Diff line number Diff line Loading @@ -66,6 +66,9 @@ #define QPNP_PON_S3_DBC_CTL(base) (base + 0x75) #define QPNP_PON_TRIGGER_EN(base) (base + 0x80) #define QPNP_PON_XVDD_RB_SPARE(base) (base + 0x8E) #define QPNP_PON_SEC_ACCESS(base) (base + 0xD0) #define QPNP_PON_SEC_UNLOCK 0xA5 #define QPNP_PON_WARM_RESET_TFT BIT(4) Loading Loading @@ -1541,6 +1544,15 @@ static int qpnp_pon_probe(struct spmi_device *spmi) /* 0 is a special value to indicate instant s3 reset */ if (s3_debounce != 0) s3_debounce = ilog2(s3_debounce); /* s3 debounce is SEC_ACCESS register */ rc = qpnp_pon_masked_write(pon, QPNP_PON_SEC_ACCESS(pon->base), 0xFF, QPNP_PON_SEC_UNLOCK); if (rc) { dev_err(&spmi->dev, "Unable to do SEC_ACCESS\n"); return rc; } rc = qpnp_pon_masked_write(pon, QPNP_PON_S3_DBC_CTL(pon->base), QPNP_PON_S3_DBC_DELAY_MASK, s3_debounce); if (rc) { Loading