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Commit 986d6c1e authored by Yi Li's avatar Yi Li Committed by Mike Frysinger
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Blackfin: drop BF535-specific text for exception 0x2A (unaligned instruction) 



We don't support the BF535 at all, and the exception 0x2A text specific to
it is pretty verbose and confusing (since the behavior is simply odd), so
punt it to keep the noise down.

Signed-off-by: default avatarYi Li <yi.li@analog.com>
Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
parent bd854c07

arch/blackfin/include/asm/traps.h

+1 −3
Original line number Original line Diff line number Diff line
@@ -111,9 +111,7 @@ 
	level "   bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"

	level "   bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"

#define EXC_0x2A(level) \

#define EXC_0x2A(level) \

	"Instruction fetch misaligned address violation\n" \

	"Instruction fetch misaligned address violation\n" \

	level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \

	level " - Attempted misaligned instruction cache fetch.\n"

	level "   exception, the return address provided in RETX is the destination address which is\n" \

	level "   misaligned, rather than the address of the offending instruction.\n"

#define EXC_0x2B(level) \

#define EXC_0x2B(level) \

	"CPLB protection violation\n" \

	"CPLB protection violation\n" \

	level " - Illegal instruction fetch access (memory protection violation).\n"

	level " - Illegal instruction fetch access (memory protection violation).\n"