Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 983379e8 authored by Yan He's avatar Yan He
Browse files

msm: pcie: add IPC logging for PCIe driver 



Add the IPC logging for PCIe driver and update the current
logging macros.

CRs-fixed: 662278
Change-Id: Ib1584ec7fb59f2005b3e8c46b70fb4c1bbedea46
Signed-off-by: default avatarYan He <yanhe@codeaurora.org>
parent f0a37c46

arch/arm/mach-msm/pcie.c

+266 −213

File changed.

Preview size limit exceeded, changes collapsed.

arch/arm/mach-msm/pcie.h

+20 −2
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 


#include <linux/clk.h>

#include <linux/compiler.h>

#include <linux/ipc_logging.h>

#include <linux/platform_device.h>

#include <linux/regulator/consumer.h>

#include <linux/types.h>
@@ -36,9 +37,25 @@ 


#define PCIE_MSI_NR_IRQS 256



#define PCIE_DBG(x...) do {              \

#define PCIE_LOG_PAGES (50)



#define PCIE_DBG(dev, fmt, arg...) do {			 \

	if ((dev) && (dev)->ipc_log)   \

		ipc_log_string((dev)->ipc_log, "%s: " fmt, __func__, arg); \

	if (msm_pcie_get_debug_mask())   \

		pr_alert(x);              \

		pr_alert("%s: " fmt, __func__, arg);              \

	} while (0)



#define PCIE_INFO(dev, fmt, arg...) do {			 \

	if ((dev) && (dev)->ipc_log)   \

		ipc_log_string((dev)->ipc_log, "%s: " fmt, __func__, arg); \

	pr_info("%s: " fmt, __func__, arg);  \

	} while (0)



#define PCIE_ERR(dev, fmt, arg...) do {			 \

	if ((dev) && (dev)->ipc_log)   \

		ipc_log_string((dev)->ipc_log, "%s: " fmt, __func__, arg); \

	pr_err("%s: " fmt, __func__, arg);  \

	} while (0)



#define PCIE_BUS_PRIV_DATA(pdev) \
@@ -209,6 +226,7 @@ struct msm_pcie_dev_t { 
	bool                         shadow_en;

	struct msm_pcie_register_event *event_reg;

	bool                         power_on;

	void                         *ipc_log;

};



extern int msm_pcie_enumerate(u32 rc_idx);

arch/arm/mach-msm/pcie_irq.c

+83 −79
Original line number Diff line number Diff line
@@ -52,11 +52,11 @@ static int msm_pcie_recover_link(struct msm_pcie_dev_t *dev) 
	ret = msm_pcie_enable(dev, PM_PIPE_CLK | PM_CLK | PM_VREG);



	if (!ret) {

		PCIE_DBG("Recover config space of RC%d and its EP\n",

		PCIE_DBG(dev, "Recover config space of RC%d and its EP\n",

				dev->rc_idx);

		PCIE_DBG("Recover RC%d\n", dev->rc_idx);

		PCIE_DBG(dev, "Recover RC%d\n", dev->rc_idx);

		msm_pcie_cfg_recover(dev, true);

		PCIE_DBG("Recover EP of RC%d\n", dev->rc_idx);

		PCIE_DBG(dev, "Recover EP of RC%d\n", dev->rc_idx);

		msm_pcie_cfg_recover(dev, false);

		dev->shadow_en = true;
@@ -67,7 +67,8 @@ static int msm_pcie_recover_link(struct msm_pcie_dev_t *dev) 
					&dev->event_reg->notify;

			notify->event = MSM_PCIE_EVENT_LINKUP;

			notify->user = dev->event_reg->user;

			PCIE_DBG("Linkup callback for RC%d\n", dev->rc_idx);

			PCIE_DBG(dev, "Linkup callback for RC%d\n",

				dev->rc_idx);

			dev->event_reg->callback(notify);

		}

	}
@@ -82,19 +83,20 @@ static void msm_pcie_notify_linkdown(struct msm_pcie_dev_t *dev) 
		struct msm_pcie_notify *notify = &dev->event_reg->notify;

		notify->event = MSM_PCIE_EVENT_LINKDOWN;

		notify->user = dev->event_reg->user;

		PCIE_DBG("PCIe: Linkdown callback for RC%d\n", dev->rc_idx);

		PCIE_DBG(dev, "PCIe: Linkdown callback for RC%d\n",

			dev->rc_idx);

		dev->event_reg->callback(notify);



		if (dev->event_reg->options & MSM_PCIE_CONFIG_NO_RECOVERY) {

			dev->user_suspend = true;

			PCIE_DBG(

			PCIE_DBG(dev,

				"PCIe: Client of RC%d will recover the link later.\n",

				dev->rc_idx);

			return;

		}



		if (dev->link_status == MSM_PCIE_LINK_DISABLED) {

			PCIE_DBG(

			PCIE_DBG(dev,

				"PCIe: Client of RC%d does not enable link in callback; so disable the link\n",

				dev->rc_idx);

			dev->recovery_pending = true;
@@ -102,12 +104,13 @@ static void msm_pcie_notify_linkdown(struct msm_pcie_dev_t *dev) 
				PM_EXPT | PM_PIPE_CLK | PM_CLK | PM_VREG);

		} else {

			dev->recovery_pending = false;

			PCIE_DBG(

			PCIE_DBG(dev,

				"PCIe: Client of RC%d has enabled link in callback; so recover config space\n",

				dev->rc_idx);

			PCIE_DBG("PCIe: Recover RC%d\n", dev->rc_idx);

			PCIE_DBG(dev, "PCIe: Recover RC%d\n", dev->rc_idx);

			msm_pcie_cfg_recover(dev, true);

			PCIE_DBG("PCIe: Recover EP of RC%d\n", dev->rc_idx);

			PCIE_DBG(dev, "PCIe: Recover EP of RC%d\n",

				dev->rc_idx);

			msm_pcie_cfg_recover(dev, false);

			dev->shadow_en = true;
@@ -119,13 +122,14 @@ static void msm_pcie_notify_linkdown(struct msm_pcie_dev_t *dev) 
						&dev->event_reg->notify;

				notify->event = MSM_PCIE_EVENT_LINKUP;

				notify->user = dev->event_reg->user;

				PCIE_DBG("PCIe: Linkup callback for RC%d\n",

				PCIE_DBG(dev,

					"PCIe: Linkup callback for RC%d\n",

					dev->rc_idx);

				dev->event_reg->callback(notify);

			}

		}

	} else {

		pr_err(

		PCIE_ERR(dev,

			"PCIe: Client driver does not have registration and this linkdown of RC%d should never happen.\n",

			dev->rc_idx);

	}
@@ -137,14 +141,14 @@ static void handle_wake_func(struct work_struct *work) 
	struct msm_pcie_dev_t *dev = container_of(work, struct msm_pcie_dev_t,

					handle_wake_work);



	PCIE_DBG("PCIe: Wake work for RC%d\n", dev->rc_idx);

	PCIE_DBG(dev, "PCIe: Wake work for RC%d\n", dev->rc_idx);



	if (!dev->enumerated) {

		mutex_lock(&dev->recovery_lock);

		ret = msm_pcie_enumerate(dev->rc_idx);

		mutex_unlock(&dev->recovery_lock);

		if (ret) {

			pr_err(

			PCIE_ERR(dev,

				"PCIe: failed to enable RC%d upon wake request from the device.\n",

				dev->rc_idx);

			return;
@@ -157,7 +161,7 @@ static void handle_wake_func(struct work_struct *work) 
					&dev->event_reg->notify;

			notify->event = MSM_PCIE_EVENT_LINKUP;

			notify->user = dev->event_reg->user;

			PCIE_DBG(

			PCIE_DBG(dev,

				"PCIe: Linkup callback for RC%d after enumeration is successful in wake IRQ handling\n",

				dev->rc_idx);

			dev->event_reg->callback(notify);
@@ -174,18 +178,18 @@ static void handle_wake_func(struct work_struct *work) 
		}



		if (waiting_cycle == LINKDOWN_WAITING_COUNT)

			pr_err(

			PCIE_ERR(dev,

				"PCIe: Linkdown handling for RC%d is not finished after max waiting time.\n",

				dev->rc_idx);



		mutex_lock(&dev->recovery_lock);

		if (dev->link_status == MSM_PCIE_LINK_ENABLED) {

			PCIE_DBG(

			PCIE_DBG(dev,

				"PCIe: The link status of RC%d is up. Check if it is really up.\n",

					dev->rc_idx);



			if (msm_pcie_confirm_linkup(dev)) {

				PCIE_DBG(

				PCIE_DBG(dev,

					"PCIe: The link status of RC%d is really up; so ignore wake IRQ.\n",

					dev->rc_idx);

				goto out;
@@ -196,36 +200,37 @@ static void handle_wake_func(struct work_struct *work) 
				gpio_set_value(

					dev->gpio[MSM_PCIE_GPIO_PERST].num,

					dev->gpio[MSM_PCIE_GPIO_PERST].on);

				pr_err(

				PCIE_ERR(dev,

					"PCIe: The link of RC%d is actually down; notify the client.\n",

					dev->rc_idx);



				msm_pcie_notify_linkdown(dev);

			}

		} else {

			PCIE_DBG("PCIe: The link status of RC%d is down.\n",

			PCIE_DBG(dev,

				"PCIe: The link status of RC%d is down.\n",

				dev->rc_idx);



			if (dev->recovery_pending) {

				static u32 retries = 1;

				PCIE_DBG(

				PCIE_DBG(dev,

					"PCIe: Start recovering link for RC%d after receive wake IRQ.\n",

					dev->rc_idx);

				ret = msm_pcie_recover_link(dev);

				if (ret) {

					pr_err(

					PCIE_ERR(dev,

						"PCIe:failed to enable link for RC%d in No. %d try after receive wake IRQ.\n",

						dev->rc_idx, retries++);

					goto out;

				} else {

					dev->recovery_pending = false;

					PCIE_DBG(

					PCIE_DBG(dev,

						"PCIe: Successful recovery for RC%d in No. %d try.\n",

						dev->rc_idx, retries);

					retries = 1;

				}

			} else if (dev->user_suspend) {

				PCIE_DBG(

				PCIE_DBG(dev,

					"PCIe: wake IRQ for RC%d for a user-suspended link.\n",

					dev->rc_idx);

				if (dev->event_reg &&
@@ -236,27 +241,27 @@ static void handle_wake_func(struct work_struct *work) 
						&dev->event_reg->notify;

					nfy->event = MSM_PCIE_EVENT_WAKEUP;

					nfy->user = dev->event_reg->user;

					PCIE_DBG(

					PCIE_DBG(dev,

						"PCIe: wakeup callback for RC%d\n",

						dev->rc_idx);

					dev->event_reg->callback(nfy);

					if (dev->link_status ==

						MSM_PCIE_LINK_ENABLED)

						PCIE_DBG(

						PCIE_DBG(dev,

							"PCIe: link is enabled after wakeup callback for RC%d\n",

							dev->rc_idx);

					else

						PCIE_DBG(

						PCIE_DBG(dev,

							"PCIe: link is NOT enabled after wakeup callback for RC%d\n",

							dev->rc_idx);

				} else {

					pr_err(

					PCIE_ERR(dev,

						"PCIe: client of RC%d does not register callback for wake IRQ for a user-suspended link.\n",

						dev->rc_idx);

				}

				goto out;

			} else {

				PCIE_DBG(

				PCIE_DBG(dev,

					"PCIe: No pending recovery or user-issued suspend for RC%d; so ignore wake IRQ.\n",

					dev->rc_idx);

				goto out;
@@ -273,16 +278,17 @@ static irqreturn_t handle_wake_irq(int irq, void *data) 
	struct msm_pcie_dev_t *dev = data;



	dev->wake_counter++;

	PCIE_DBG("PCIe: No. %ld wake IRQ for RC%d\n",

	PCIE_DBG(dev, "PCIe: No. %ld wake IRQ for RC%d\n",

			dev->wake_counter, dev->rc_idx);



	PCIE_DBG("PCIe WAKE is asserted by Endpoint of RC%d\n", dev->rc_idx);

	PCIE_DBG(dev, "PCIe WAKE is asserted by Endpoint of RC%d\n",

		dev->rc_idx);



	if (!dev->enumerated) {

		PCIE_DBG("Start enumeating RC%d\n", dev->rc_idx);

		PCIE_DBG(dev, "Start enumeating RC%d\n", dev->rc_idx);

		schedule_work(&dev->handle_wake_work);

	} else {

		PCIE_DBG("Wake up RC%d\n", dev->rc_idx);

		PCIE_DBG(dev, "Wake up RC%d\n", dev->rc_idx);

		__pm_stay_awake(&dev->ws);

		__pm_relax(&dev->ws);
@@ -297,12 +303,12 @@ static void handle_linkdown_func(struct work_struct *work) 
	struct msm_pcie_dev_t *dev = container_of(work, struct msm_pcie_dev_t,

					handle_linkdown_work);



	PCIE_DBG("PCIe: Linkdown work for RC%d\n", dev->rc_idx);

	PCIE_DBG(dev, "PCIe: Linkdown work for RC%d\n", dev->rc_idx);



	mutex_lock(&dev->recovery_lock);



	if (msm_pcie_confirm_linkup(dev))

		PCIE_DBG(

		PCIE_DBG(dev,

			"PCIe: The link status of RC%d is up now, indicating recovery has been done.\n",

			dev->rc_idx);

	else
@@ -310,7 +316,7 @@ static void handle_linkdown_func(struct work_struct *work) 


	dev->handling_linkdown--;

	if (dev->handling_linkdown < 0)

		pr_err("PCIe:handling_linkdown for RC%d is %d\n",

		PCIE_ERR(dev, "PCIe:handling_linkdown for RC%d is %d\n",

			dev->rc_idx, dev->handling_linkdown);

	mutex_unlock(&dev->recovery_lock);

}
@@ -321,15 +327,16 @@ static irqreturn_t handle_linkdown_irq(int irq, void *data) 


	dev->linkdown_counter++;

	dev->handling_linkdown++;

	PCIE_DBG("PCIe: No. %ld linkdown IRQ for RC%d: handling_linkdown:%d\n",

	PCIE_DBG(dev,

		"PCIe: No. %ld linkdown IRQ for RC%d: handling_linkdown:%d\n",

		dev->linkdown_counter, dev->rc_idx, dev->handling_linkdown);



	if (!dev->enumerated || dev->link_status != MSM_PCIE_LINK_ENABLED) {

		PCIE_DBG(

		PCIE_DBG(dev,

			"PCIe:Linkdown IRQ for RC%d when the link is not enabled\n",

			dev->rc_idx);

	} else if (dev->suspending) {

		PCIE_DBG(

		PCIE_DBG(dev,

			"PCIe:the link of RC%d is suspending.\n",

			dev->rc_idx);

	} else {
@@ -338,7 +345,7 @@ static irqreturn_t handle_linkdown_irq(int irq, void *data) 
		/* assert PERST */

		gpio_set_value(dev->gpio[MSM_PCIE_GPIO_PERST].num,

				dev->gpio[MSM_PCIE_GPIO_PERST].on);

		pr_err("PCIe link is down for RC%d\n", dev->rc_idx);

		PCIE_ERR(dev, "PCIe link is down for RC%d\n", dev->rc_idx);

		schedule_work(&dev->handle_linkdown_work);

	}
@@ -352,7 +359,7 @@ static irqreturn_t handle_msi_irq(int irq, void *data) 
	struct msm_pcie_dev_t *dev = data;

	void __iomem *ctrl_status;



	PCIE_DBG("\n");

	PCIE_DBG(dev, "irq=%d\n", irq);



	/* check for set bits, clear it by setting that bit

	   and trigger corresponding irq */
@@ -380,7 +387,7 @@ void msm_pcie_config_msi_controller(struct msm_pcie_dev_t *dev) 
{

	int i;



	PCIE_DBG("RC%d\n", dev->rc_idx);

	PCIE_DBG(dev, "RC%d\n", dev->rc_idx);



	/* program MSI controller and enable all interrupts */

	writel_relaxed(MSM_PCIE_MSI_PHY, dev->dm_core + PCIE20_MSI_CTRL_ADDR);
@@ -405,29 +412,29 @@ void msm_pcie_destroy_irq(unsigned int irq, struct msm_pcie_dev_t *pcie_dev) 
		dev = irq_get_chip_data(irq);



	if (dev->msi_gicm_addr) {

		PCIE_DBG("destroy QGIC based irq\n");

		PCIE_DBG(dev, "destroy QGIC based irq %d\n", irq);

		pos = irq - dev->msi_gicm_base;

	} else {

		PCIE_DBG("destroy default MSI irq\n");

		PCIE_DBG(dev, "destroy default MSI irq %d\n", irq);

		pos = irq - irq_find_mapping(dev->irq_domain, 0);

	}



	PCIE_DBG("RC%d\n", dev->rc_idx);

	PCIE_DBG(dev, "RC%d\n", dev->rc_idx);



	if (!dev->msi_gicm_addr)

		dynamic_irq_cleanup(irq);



	PCIE_DBG("Before clear_bit pos:%d msi_irq_in_use:%ld\n",

	PCIE_DBG(dev, "Before clear_bit pos:%d msi_irq_in_use:%ld\n",

		pos, *dev->msi_irq_in_use);

	clear_bit(pos, dev->msi_irq_in_use);

	PCIE_DBG("After clear_bit pos:%d msi_irq_in_use:%ld\n",

	PCIE_DBG(dev, "After clear_bit pos:%d msi_irq_in_use:%ld\n",

		pos, *dev->msi_irq_in_use);

}



/* hookup to linux pci msi framework */

void arch_teardown_msi_irq(unsigned int irq)

{

	PCIE_DBG("irq %d deallocated\n", irq);

	pr_debug("irq %d deallocated\n", irq);

	msm_pcie_destroy_irq(irq, NULL);

}
@@ -436,7 +443,7 @@ void arch_teardown_msi_irqs(struct pci_dev *dev) 
	struct msi_desc *entry;

	struct msm_pcie_dev_t *pcie_dev = PCIE_BUS_PRIV_DATA(dev);



	PCIE_DBG("RC:%d EP: vendor_id:0x%x device_id:0x%x\n",

	PCIE_DBG(pcie_dev, "RC:%d EP: vendor_id:0x%x device_id:0x%x\n",

		pcie_dev->rc_idx, dev->vendor, dev->device);



	list_for_each_entry(entry, &dev->msi_list, list) {
@@ -451,7 +458,6 @@ void arch_teardown_msi_irqs(struct pci_dev *dev) 


static void msm_pcie_msi_nop(struct irq_data *d)

{

	PCIE_DBG("\n");

	return;

}
@@ -468,7 +474,7 @@ static int msm_pcie_create_irq(struct msm_pcie_dev_t *dev) 
{

	int irq, pos;



	PCIE_DBG("RC%d\n", dev->rc_idx);

	PCIE_DBG(dev, "RC%d\n", dev->rc_idx);



again:

	pos = find_first_zero_bit(dev->msi_irq_in_use, PCIE_MSI_NR_IRQS);
@@ -476,12 +482,12 @@ again: 
	if (pos >= PCIE_MSI_NR_IRQS)

		return -ENOSPC;



	PCIE_DBG("pos:%d msi_irq_in_use:%ld\n", pos, *dev->msi_irq_in_use);

	PCIE_DBG(dev, "pos:%d msi_irq_in_use:%ld\n", pos, *dev->msi_irq_in_use);



	if (test_and_set_bit(pos, dev->msi_irq_in_use))

		goto again;

	else

		PCIE_DBG("test_and_set_bit is successful\n");

		PCIE_DBG(dev, "test_and_set_bit is successful pos=%d\n", pos);



	irq = irq_create_mapping(dev->irq_domain, pos);

	if (!irq)
@@ -497,16 +503,16 @@ static int arch_setup_msi_irq_default(struct pci_dev *pdev, 
	struct msi_msg msg;

	struct msm_pcie_dev_t *dev = PCIE_BUS_PRIV_DATA(pdev);



	PCIE_DBG("RC%d\n", dev->rc_idx);

	PCIE_DBG(dev, "RC%d\n", dev->rc_idx);



	irq = msm_pcie_create_irq(dev);



	PCIE_DBG("IRQ %d is allocated.\n", irq);

	PCIE_DBG(dev, "IRQ %d is allocated.\n", irq);



	if (irq < 0)

		return irq;



	PCIE_DBG("irq %d allocated\n", irq);

	PCIE_DBG(dev, "irq %d allocated\n", irq);



	irq_set_msi_desc(irq, desc);
@@ -523,7 +529,7 @@ static int msm_pcie_create_irq_qgic(struct msm_pcie_dev_t *dev) 
{

	int irq, pos;



	PCIE_DBG("RC%d\n", dev->rc_idx);

	PCIE_DBG(dev, "RC%d\n", dev->rc_idx);



again:

	pos = find_first_zero_bit(dev->msi_irq_in_use, PCIE_MSI_NR_IRQS);
@@ -531,16 +537,16 @@ again: 
	if (pos >= PCIE_MSI_NR_IRQS)

		return -ENOSPC;



	PCIE_DBG("pos:%d msi_irq_in_use:%ld\n", pos, *dev->msi_irq_in_use);

	PCIE_DBG(dev, "pos:%d msi_irq_in_use:%ld\n", pos, *dev->msi_irq_in_use);



	if (test_and_set_bit(pos, dev->msi_irq_in_use))

		goto again;

	else

		PCIE_DBG("test_and_set_bit is successful\n");

		PCIE_DBG(dev, "test_and_set_bit is successful pos=%d\n", pos);



	irq = dev->msi_gicm_base + pos;

	if (!irq) {

		pr_err("PCIe: RC%d failed to create QGIC MSI IRQ.\n",

		PCIE_ERR(dev, "PCIe: RC%d failed to create QGIC MSI IRQ.\n",

			dev->rc_idx);

		return -EINVAL;

	}
@@ -555,11 +561,11 @@ static int arch_setup_msi_irq_qgic(struct pci_dev *pdev, 
	struct msi_msg msg;

	struct msm_pcie_dev_t *dev = PCIE_BUS_PRIV_DATA(pdev);



	PCIE_DBG("RC%d\n", dev->rc_idx);

	PCIE_DBG(dev, "RC%d\n", dev->rc_idx);



	for (index = 0; index < nvec; index++) {

		irq = msm_pcie_create_irq_qgic(dev);

		PCIE_DBG("irq %d is allocated\n", irq);

		PCIE_DBG(dev, "irq %d is allocated\n", irq);



		if (irq < 0)

			return irq;
@@ -584,7 +590,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) 
{

	struct msm_pcie_dev_t *dev = PCIE_BUS_PRIV_DATA(pdev);



	PCIE_DBG("RC%d\n", dev->rc_idx);

	PCIE_DBG(dev, "RC%d\n", dev->rc_idx);



	if (dev->msi_gicm_addr)

		return arch_setup_msi_irq_qgic(pdev, desc, 1);
@@ -596,13 +602,11 @@ static int msm_pcie_get_msi_multiple(int nvec) 
{

	int msi_multiple = 0;



	PCIE_DBG("\n");



	while (nvec) {

		nvec = nvec >> 1;

		msi_multiple++;

	}

	PCIE_DBG("log2 number of MSI multiple:%d\n",

	pr_debug("log2 number of MSI multiple:%d\n",

		msi_multiple - 1);



	return msi_multiple - 1;
@@ -614,12 +618,12 @@ int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) 
	int ret;

	struct msm_pcie_dev_t *pcie_dev = PCIE_BUS_PRIV_DATA(dev);



	PCIE_DBG("RC%d\n", pcie_dev->rc_idx);

	PCIE_DBG(pcie_dev, "RC%d\n", pcie_dev->rc_idx);



	if (type != PCI_CAP_ID_MSI || nvec > 32)

		return -ENOSPC;



	PCIE_DBG("nvec = %d\n", nvec);

	PCIE_DBG(pcie_dev, "nvec = %d\n", nvec);



	list_for_each_entry(entry, &dev->msi_list, list) {

		entry->msi_attrib.multiple =
@@ -630,7 +634,7 @@ int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) 
		else

			ret = arch_setup_msi_irq_default(dev, entry, nvec);



		PCIE_DBG("ret from msi_irq: %d\n", ret);

		PCIE_DBG(pcie_dev, "ret from msi_irq: %d\n", ret);



		if (ret < 0)

			return ret;
@@ -644,7 +648,6 @@ int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) 
static int msm_pcie_msi_map(struct irq_domain *domain, unsigned int irq,

	   irq_hw_number_t hwirq)

{

	PCIE_DBG("\n");

	irq_set_chip_and_handler (irq, &pcie_msi_chip, handle_simple_irq);

	irq_set_chip_data(irq, domain->host_data);

	set_irq_flags(irq, IRQF_VALID);
@@ -661,7 +664,7 @@ int32_t msm_pcie_irq_init(struct msm_pcie_dev_t *dev) 
	int msi_start =  0;

	struct device *pdev = &dev->pdev->dev;



	PCIE_DBG("RC%d\n", dev->rc_idx);

	PCIE_DBG(dev, "RC%d\n", dev->rc_idx);



	wakeup_source_init(&dev->ws, "pcie_wakeup_source");
@@ -671,7 +674,7 @@ int32_t msm_pcie_irq_init(struct msm_pcie_dev_t *dev) 
		IRQF_TRIGGER_RISING, dev->irq[MSM_PCIE_INT_LINK_DOWN].name,

		dev);

	if (rc) {

		pr_err("PCIe: Unable to request linkdown interrupt:%d\n",

		PCIE_ERR(dev, "PCIe: Unable to request linkdown interrupt:%d\n",

			dev->irq[MSM_PCIE_INT_LINK_DOWN].num);

		return rc;

	}
@@ -683,7 +686,7 @@ int32_t msm_pcie_irq_init(struct msm_pcie_dev_t *dev) 
		dev->irq[MSM_PCIE_INT_MSI].num, handle_msi_irq,

		IRQF_TRIGGER_RISING, dev->irq[MSM_PCIE_INT_MSI].name, dev);

	if (rc) {

		pr_err("PCIe: RC%d: Unable to request MSI interrupt\n",

		PCIE_ERR(dev, "PCIe: RC%d: Unable to request MSI interrupt\n",

			dev->rc_idx);

		return rc;

	}
@@ -693,7 +696,7 @@ int32_t msm_pcie_irq_init(struct msm_pcie_dev_t *dev) 
			dev->wake_n, handle_wake_irq, IRQF_TRIGGER_FALLING,

			 "msm_pcie_wake", dev);

	if (rc) {

		pr_err("PCIe: RC%d: Unable to request wake interrupt\n",

		PCIE_ERR(dev, "PCIe: RC%d: Unable to request wake interrupt\n",

			dev->rc_idx);

		return rc;

	}
@@ -702,7 +705,7 @@ int32_t msm_pcie_irq_init(struct msm_pcie_dev_t *dev) 


	rc = enable_irq_wake(dev->wake_n);

	if (rc) {

		pr_err("PCIe: RC%d: Unable to enable wake interrupt\n",

		PCIE_ERR(dev, "PCIe: RC%d: Unable to enable wake interrupt\n",

			dev->rc_idx);

		return rc;

	}
@@ -713,7 +716,8 @@ int32_t msm_pcie_irq_init(struct msm_pcie_dev_t *dev) 
			PCIE_MSI_NR_IRQS, &msm_pcie_msi_ops, dev);



		if (!dev->irq_domain) {

			pr_err("PCIe: RC%d: Unable to initialize irq domain\n",

			PCIE_ERR(dev,

				"PCIe: RC%d: Unable to initialize irq domain\n",

				dev->rc_idx);

			disable_irq(dev->wake_n);

			return PTR_ERR(dev->irq_domain);
@@ -727,7 +731,7 @@ int32_t msm_pcie_irq_init(struct msm_pcie_dev_t *dev) 


void msm_pcie_irq_deinit(struct msm_pcie_dev_t *dev)

{

	PCIE_DBG("RC%d\n", dev->rc_idx);

	PCIE_DBG(dev, "RC%d\n", dev->rc_idx);



	wakeup_source_trash(&dev->ws);

	disable_irq(dev->wake_n);

arch/arm/mach-msm/pcie_phy.c

+6 −3
Original line number Diff line number Diff line
@@ -29,7 +29,8 @@ static inline void write_phy(void *base, u32 offset, u32 value) 
static inline void pcie20_phy_init_default(struct msm_pcie_dev_t *dev)

{



	PCIE_DBG("Initializing 28nm QMP phy - 19.2MHz\n");

	PCIE_DBG(dev, "RC%d: Initializing 28nm QMP phy - 19.2MHz\n",

		dev->rc_idx);



	write_phy(dev->phy, PCIE_PHY_POWER_DOWN_CONTROL,		0x03);

	write_phy(dev->phy, QSERDES_COM_SYSCLK_EN_SEL,		0x08);
@@ -63,7 +64,8 @@ static inline void pcie20_phy_init_default(struct msm_pcie_dev_t *dev) 
void pcie_phy_init(struct msm_pcie_dev_t *dev)

{



	PCIE_DBG("Initializing 28nm QMP phy - 19.2MHz\n");

	PCIE_DBG(dev, "RC%d: Initializing 28nm QMP phy - 19.2MHz\n",

		dev->rc_idx);



	write_phy(dev->phy, PCIE_PHY_POWER_DOWN_CONTROL, 0x03);
@@ -126,7 +128,8 @@ void pcie_phy_init(struct msm_pcie_dev_t *dev) 
		return;

	}



	PCIE_DBG("Initializing 28nm ATE phy - 100MHz\n");

	PCIE_DBG(dev, "RC%d: Initializing 28nm ATE phy - 100MHz\n",

		dev->rc_idx);



	/*  1 */

	write_phy(dev->phy, PCIE_PHY_POWER_DOWN_CONTROL, 0x01);