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Commit 95f5e237 authored by Tianyi Gou's avatar Tianyi Gou
Browse files

qcom: soc: pil-q6v5: Add support for qdsp6v56.1.3 reset 



On the new qdsp6v56 1.3 version HW, the reset sequence for turning
on the memory has changed. Add a version flag to the subsystem's
dt entry to indicate this minor version and select the corresponding
reset sequence for this version.

Change-Id: I645ceb84493a6970390a4271407ddb6c5e829f9e
Signed-off-by: default avatarTianyi Gou <tgou@codeaurora.org>
parent 4047daa3

Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt

+1 −0
Original line number Diff line number Diff line
@@ -59,6 +59,7 @@ Optional properties: 
- qcom,override-acc: Boolean- Present if we need to override the default ACC settings

- qcom,ahb-clk-vote: Boolean- Present if we need to remove the vote for the mss_cfg_ahb

		     clock after the modem boots up

- qcom,qdsp6v56-1-3: Boolean- Present if the qdsp version is v56 1.3



Example:

	qcom,mss@fc880000 {

drivers/soc/qcom/pil-q6v5.c

+26 −8
Original line number Diff line number Diff line
@@ -300,7 +300,8 @@ static int q6v55_branch_clk_enable(struct q6v5_data *drv) 
static int __pil_q6v55_reset(struct pil_desc *pil)

{

	struct q6v5_data *drv = container_of(pil, struct q6v5_data, desc);

	u32 val, i;

	u32 val;

	int i;



	/* Override the ACC value if required */

	if (drv->override_acc)
@@ -326,6 +327,19 @@ static int __pil_q6v55_reset(struct pil_desc *pil) 
	val |= QDSP6v55_LDO_BYP;

	writel_relaxed(val, drv->reg_base + QDSP6SS_PWR_CTL);



	if (drv->qdsp6v56_1_3) {

		/* Deassert memory peripheral sleep and L2 memory standby */

		val = readl_relaxed(drv->reg_base + QDSP6SS_PWR_CTL);

		val |= (Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N);

		writel_relaxed(val, drv->reg_base + QDSP6SS_PWR_CTL);



		/* Turn on L1, L2 and ETB memories 1 at a time */

		for (i = 17; i >= 0; i--) {

			val |= BIT(i);

			writel_relaxed(val, drv->reg_base + QDSP6SS_PWR_CTL);

			udelay(1);

		}

	} else {

		/* Turn on memories. */

		val = readl_relaxed(drv->reg_base + QDSP6SS_PWR_CTL);

		val |= 0xFFF00;
@@ -336,6 +350,7 @@ static int __pil_q6v55_reset(struct pil_desc *pil) 
			val |= BIT(i);

			writel_relaxed(val, drv->reg_base + QDSP6SS_PWR_CTL);

		}

	}



	/* Remove word line clamp */

	val &= ~QDSP6v55_CLAMP_WL;
@@ -454,6 +469,9 @@ struct q6v5_data *pil_q6v5_init(struct platform_device *pdev) 
	drv->qdsp6v56 = of_device_is_compatible(pdev->dev.of_node,

						"qcom,pil-q6v56-mss");



	drv->qdsp6v56_1_3 = of_property_read_bool(pdev->dev.of_node,

						"qcom,qdsp6v56-1-3");



	drv->non_elf_image = of_property_read_bool(pdev->dev.of_node,

						"qcom,mba-image-is-not-elf");

drivers/soc/qcom/pil-q6v5.h

+1 −0
Original line number Diff line number Diff line
@@ -50,6 +50,7 @@ struct q6v5_data { 
	bool qdsp6v55;

	bool qdsp6v5_2_0;

	bool qdsp6v56;

	bool qdsp6v56_1_3;

	bool non_elf_image;

	bool restart_reg_sec;

	bool override_acc;