Loading Documentation/devicetree/bindings/arm/msm/spm-regulator.txt +2 −0 Original line number Diff line number Diff line Loading @@ -18,6 +18,8 @@ Optional properties: robust, but draws more current than auto mode. If this property is not specified, then the regulator will remain in whatever mode hardware or bootloaders set it to. - qcom,cpu-num: Specifies which CPU this regulator powers. This property is not need when the SPM regulator is shared between all CPUs. All properties specified within the core regulator framework can also be used. These bindings can be found in regulator.txt. Loading arch/arm/mach-msm/spm-regulator.c +7 −1 Original line number Diff line number Diff line Loading @@ -90,6 +90,7 @@ struct spm_vreg { u16 spmi_base_addr; u8 init_mode; int step_rate; u32 cpu_num; }; static int qpnp_fts2_set_mode(struct spm_vreg *vreg, u8 mode) Loading Loading @@ -121,7 +122,7 @@ static int _spm_regulator_set_voltage(struct regulator_dev *rdev) return rc; } rc = msm_spm_set_vdd(0, vreg->vlevel); /* value of CPU is don't care */ rc = msm_spm_set_vdd(vreg->cpu_num, vreg->vlevel); if (rc) { pr_err("%s: msm_spm_set_vdd failed %d\n", vreg->rdesc.name, rc); return rc; Loading Loading @@ -415,6 +416,11 @@ static int spm_regulator_probe(struct spmi_device *spmi) if (rc) return rc; /* Specify CPU 0 as default in order to handle shared regulator case. */ vreg->cpu_num = 0; of_property_read_u32(vreg->spmi_dev->dev.of_node, "qcom,cpu-num", &vreg->cpu_num); /* * The FTS2 regulator must be initialized to range 0 or range 1 during * PMIC power on sequence. Once it is set, it cannot be changed Loading Loading
Documentation/devicetree/bindings/arm/msm/spm-regulator.txt +2 −0 Original line number Diff line number Diff line Loading @@ -18,6 +18,8 @@ Optional properties: robust, but draws more current than auto mode. If this property is not specified, then the regulator will remain in whatever mode hardware or bootloaders set it to. - qcom,cpu-num: Specifies which CPU this regulator powers. This property is not need when the SPM regulator is shared between all CPUs. All properties specified within the core regulator framework can also be used. These bindings can be found in regulator.txt. Loading
arch/arm/mach-msm/spm-regulator.c +7 −1 Original line number Diff line number Diff line Loading @@ -90,6 +90,7 @@ struct spm_vreg { u16 spmi_base_addr; u8 init_mode; int step_rate; u32 cpu_num; }; static int qpnp_fts2_set_mode(struct spm_vreg *vreg, u8 mode) Loading Loading @@ -121,7 +122,7 @@ static int _spm_regulator_set_voltage(struct regulator_dev *rdev) return rc; } rc = msm_spm_set_vdd(0, vreg->vlevel); /* value of CPU is don't care */ rc = msm_spm_set_vdd(vreg->cpu_num, vreg->vlevel); if (rc) { pr_err("%s: msm_spm_set_vdd failed %d\n", vreg->rdesc.name, rc); return rc; Loading Loading @@ -415,6 +416,11 @@ static int spm_regulator_probe(struct spmi_device *spmi) if (rc) return rc; /* Specify CPU 0 as default in order to handle shared regulator case. */ vreg->cpu_num = 0; of_property_read_u32(vreg->spmi_dev->dev.of_node, "qcom,cpu-num", &vreg->cpu_num); /* * The FTS2 regulator must be initialized to range 0 or range 1 during * PMIC power on sequence. Once it is set, it cannot be changed Loading