Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 94125589 authored by Vijayavardhan Vennapusa's avatar Vijayavardhan Vennapusa
Browse files

ARM: dts: msm: Add regulator & clock entries for USB node for msmtellurium 



Add regulator entries and missing clock entries for Femto PHY
and also required bus votings as well for USB device node for
msmtellurium.

Change-Id: Ida9f7bddfef693d6b919de76c7706859c5d4751f
Signed-off-by: default avatarVijayavardhan Vennapusa <vvreddy@codeaurora.org>
parent 18c43109

arch/arm/boot/dts/qcom/msmtellurium-rumi.dts

+4 −0
Original line number Diff line number Diff line
@@ -32,3 +32,7 @@ 
	pinctrl-names = "default";

	pinctrl-0 = <&uart_console_sleep>;

};



&usb_otg {

	qcom,hsusb-otg-otg-control = <1>;

};

arch/arm/boot/dts/qcom/msmtellurium.dtsi

+23 −1
Original line number Diff line number Diff line
@@ -515,6 +515,11 @@ 
		interrupts = <0 134 0>,<0 140 0>;

		interrupt-names = "core_irq", "async_irq";



		hsusb_vdd_dig-supply = <&pmtellurium_l2>;

		HSUSB_1p8-supply = <&pmtellurium_l7>;

		HSUSB_3p3-supply = <&pmtellurium_l13>;

		qcom,vdd-voltage-level = <0 1200000 1200000>;



		qcom,hsusb-otg-phy-type = <3>; /* SNPS Femto PHY */

		qcom,hsusb-otg-mode = <1>; /* DEVICE only */

		qcom,hsusb-otg-otg-control = <2>; /* PMIC */
@@ -522,13 +527,30 @@ 
		qcom,hsusb-otg-disable-reset;

		qcom,hsusb-otg-mpm-dpsehv-int = <49>;

		qcom,hsusb-otg-mpm-dmsehv-int = <58>;



		qcom,phy-dvdd-always-on;



		qcom,msm-bus,name = "usb2";

		qcom,msm-bus,num-cases = <3>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<87 512 0 0>,

				<87 512 80000 0>,

				<87 512 6000  6000>;

		clocks = <&clock_gcc clk_gcc_usb_hs_ahb_clk>,

			 <&clock_gcc clk_gcc_usb_hs_system_clk>,

			 <&clock_gcc clk_gcc_usb2a_phy_sleep_clk>,

			 <&clock_gcc clk_bimc_usb_a_clk>,

			 <&clock_gcc clk_snoc_usb_a_clk>,

			 <&clock_gcc clk_pnoc_usb_a_clk>,

			 <&clock_gcc clk_gcc_qusb2_phy_clk>,

			 <&clock_gcc clk_gcc_usb2_hs_phy_only_clk>,

			 <&clock_gcc clk_gcc_usb_hs_phy_cfg_ahb_clk>,

			 <&clock_gcc clk_xo_otg_clk>;

		clock-names = "iface_clk", "core_clk", "sleep_clk",

				"bimc_clk", "snoc_clk", "pcnoc_clk",

				"phy_reset_clk", "phy_por_clk", "phy_csr_clk",

				"xo";

		qcom,bus-clk-rate = <350400000 200000000 100000000>;

	};



	android_usb: android_usb@086000c8 {