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Commit 93f0f9bb authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Allow bus_min/_max to be set in dtsi files"

parents d94cc674 70267bc2

Documentation/devicetree/bindings/gpu/adreno-pwrlevels.txt

+7 −1
Original line number Diff line number Diff line
@@ -12,8 +12,12 @@ Each powerlevel definition is as follows: 
- reg:              Index of the power level (lower is considered higher

		    performance)

- qcom,gpu-freq:    The GPU frequency for the power level (in HZ)

- qcom,bus-freq:    An index representing the bus scaling usecase appropriate

- qcom,bus-freq:    An index representing the default bus scaling appropriate

		    for the power level

- qcom,bus-min:     An optional index representing the minimum bus scaling

		    appropriate for the power level

- qcom,bus-max:     An optional index representing the maximum bus scaling

		    appropriate for the power level



Sample usage:
@@ -29,6 +33,8 @@ qcom,kgsl-3d0@fdb00000 { 
			reg = <0>;

			qcom,gpu-freq = <5000000000>;

			qcom,bus-freq = <3>;

			qcom,bus-min = <2>;

			qcom,bus-max = <4>;

		};

	};

drivers/gpu/msm/adreno.c

+8 −0
Original line number Diff line number Diff line
@@ -874,6 +874,14 @@ static int adreno_of_get_pwrlevels(struct device_node *parent, 
		if (adreno_of_read_property(child, "qcom,bus-freq",

			&level->bus_freq))

			goto done;



		if (of_property_read_u32(child, "qcom,bus-min",

			&level->bus_min))

			level->bus_min = level->bus_freq;



		if (of_property_read_u32(child, "qcom,bus-max",

			&level->bus_max))

			level->bus_max = level->bus_freq;

	}



	if (of_property_read_u32(parent, "qcom,initial-pwrlevel",

drivers/gpu/msm/kgsl_pwrctrl.c

+19 −2
Original line number Diff line number Diff line
@@ -1041,7 +1041,7 @@ EXPORT_SYMBOL(kgsl_pwrctrl_irq); 


int kgsl_pwrctrl_init(struct kgsl_device *device)

{

	int i, k, m, n = 0, result = 0;

	int i, k, m, set_bus = 1, n = 0, result = 0;

	unsigned int freq_i, rbbmtimer_freq;

	struct clk *clk;

	struct platform_device *pdev = device->pdev;
@@ -1088,6 +1088,17 @@ int kgsl_pwrctrl_init(struct kgsl_device *device) 
					   gpu_freq) : 0;

		pwr->pwrlevels[i].bus_freq =

			pdata->pwrlevel[i].bus_freq;

		pwr->pwrlevels[i].bus_min =

			pdata->pwrlevel[i].bus_min;

		pwr->pwrlevels[i].bus_max =

			pdata->pwrlevel[i].bus_max;

		/*

		 * If the bus min/max values are specified to be something

		 * other than defaults, do not attempt to generate them

		 * below.

		 */

		if (pwr->pwrlevels[i].bus_min != pwr->pwrlevels[i].bus_max)

			set_bus = 0;

	}

	/* Do not set_rate for targets in sync with AXI */

	if (pwr->pwrlevels[0].gpu_freq > 0) {
@@ -1160,6 +1171,12 @@ int kgsl_pwrctrl_init(struct kgsl_device *device) 
			for (k = 0; k < n; k++)

				if (vector->ib == pwr->bus_ib[k]) {

					static uint64_t last_ib = 0xFFFFFFFF;

					/*

					 * if the bus min/max are already set

					 * leave them alone.

					 */

					if (set_bus == 0)

						break;

					if (vector->ib <= last_ib) {

						pwr->pwrlevels[freq_i--].

							bus_max = i - 1;
@@ -1184,7 +1201,7 @@ int kgsl_pwrctrl_init(struct kgsl_device *device) 
			}

		}

	}

	pwr->pwrlevels[freq_i].bus_max = i - 1;

	pwr->pwrlevels[0].bus_max = i - 1;



	return result;