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Commit 93e79940 authored by Pavankumar Kondeti's avatar Pavankumar Kondeti Committed by Stephen Boyd
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USB: dwc3: Add workaround for incorrect GUSB3PIPECTL default value 



GUSB3PIPECTL[22] bit is for enabling/disabling receiver detection in
either U3 or Rx.Detect states.  It should be '0' by default to enable
receiver detection.  But it is overridden with '1' on cores revision <
2.30a.  Fix this in software.

CRs-Fixed: 377848
Change-Id: I9500f687f386330ed3c686f46365c08b8c8b0d28
Signed-off-by: default avatarPavankumar Kondeti <pkondeti@codeaurora.org>
parent 2efbf243

drivers/usb/dwc3/core.c

+5 −0
Original line number Diff line number Diff line
@@ -385,6 +385,11 @@ static int dwc3_core_init(struct dwc3 *dwc) 
		reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));

		reg &= ~DWC3_GUSB3PIPECTL_DELAY_P1P2P3;

		reg |= 1 << __ffs(DWC3_GUSB3PIPECTL_DELAY_P1P2P3);

		/*

		 * Receiver Detection in U3/Rx.Det is mistakenly disabled in

		 * cores < 2.30a. Fix it here.

		 */

		reg &= ~DWC3_GUSB3PIPECTL_DIS_RXDET_U3_RXDET;

		dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);

	}

drivers/usb/dwc3/core.h

+1 −0
Original line number Diff line number Diff line
@@ -193,6 +193,7 @@ 
#define DWC3_GUSB3PIPECTL_PHYSOFTRST	(1 << 31)

#define DWC3_GUSB3PIPECTL_SUSPHY	(1 << 17)

#define DWC3_GUSB3PIPECTL_DELAY_P1P2P3	(7 << 19)

#define DWC3_GUSB3PIPECTL_DIS_RXDET_U3_RXDET (1 << 22)



/* Global TX Fifo Size Register */

#define DWC3_GTXFIFOSIZ_TXFDEF(n)	((n) & 0xffff)