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Commit 93a97f2a authored by Subbaraman Narayanamurthy's avatar Subbaraman Narayanamurthy
Browse files

msm: qpnp-power-on: program S3_TIMER register only based on DT property 



Currently, S3 timer register is getting configured even when the
corresponding device tree property is not present. For e.g. S3
timer for secondary PMIC's PON is programmed to zero causing
immediate reset of that PMIC when the power + volume down keys
are pressed. Fix this by checking that the device tree property
is available before programming the timers.

CRs-Fixed: 783553
Change-Id: Ia78f7cd78b31930783bed51c63afea6edc775ac9
Signed-off-by: default avatarSubbaraman Narayanamurthy <subbaram@codeaurora.org>
parent 42162e39

drivers/platform/msm/qpnp-power-on.c

+13 −9
Original line number Diff line number Diff line 
/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.

/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -1582,10 +1582,12 @@ static int qpnp_pon_probe(struct spmi_device *spmi) 
	/* program s3 debounce */

	rc = of_property_read_u32(pon->spmi->dev.of_node,

				"qcom,s3-debounce", &s3_debounce);

	if (rc && rc != -EINVAL) {

	if (rc) {

		if (rc != -EINVAL) {

			dev_err(&pon->spmi->dev, "Unable to read s3 timer rc:%d\n",

				rc);

			return rc;

		}

	} else {

		if (s3_debounce > QPNP_PON_S3_TIMER_SECS_MAX) {

			dev_info(&pon->spmi->dev,
@@ -1660,10 +1662,12 @@ static int qpnp_pon_probe(struct spmi_device *spmi) 


	rc = of_property_read_u32(pon->spmi->dev.of_node,

				"qcom,pon-dbc-delay", &delay);

	if (rc && rc != -EINVAL) {

	if (rc) {

		if (rc != -EINVAL) {

			dev_err(&spmi->dev, "Unable to read debounce delay rc: %d\n",

				rc);

			return rc;

		}

	} else {

		rc = qpnp_pon_set_dbc(pon, delay);

	}