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Commit 9305cdd5 authored by Gilad Avidov's avatar Gilad Avidov Committed by Stephen Boyd
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ARM: dts: msm: Update SPI entries



SPI driver has new device tree bindings for GPIOS and
for clock-path voting. Here, SPI entries are updated
to reflect these changes.

CRs-Fixed: 514669
Change-Id: I06f84f09569d5768f762f59b2811508a89cf927a
Signed-off-by: default avatarGilad Avidov <gavidov@codeaurora.org>
parent c052bc63
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+25 −8
Original line number Diff line number Diff line
@@ -10,6 +10,12 @@
 * GNU General Public License for more details.
 */

/ {
	aliases {
		spi0 = &spi_0;
	};
};

&soc {
	timer {
		clock-frequency = <5000000>;
@@ -41,17 +47,28 @@
		status = "disable";
	};

	spi@f9923000 {
	spi_0: spi@f9923000 { /* BLSP1 QUP1 */
		compatible = "qcom,spi-qup-v2";
		reg = <0xf9923000 0x1000>;
		interrupts = <0 95 0>;
		spi-max-frequency = <24000000>;
		#address-cells = <1>;
		#size-cells = <0>;
		gpios = <&msmgpio 3 0>, /* CLK  */
			<&msmgpio 1 0>, /* MISO */
			<&msmgpio 0 0>; /* MOSI */
		cs-gpios = <&msmgpio 9 0>;
		reg-names = "spi_physical", "spi_bam_physical";
		reg = <0xf9923000 0x1000>,
		      <0xf9904000 0xf000>;
		interrupt-names = "spi_irq", "spi_bam_irq";
		interrupts = <0 95 0>, <0 238 0>;
		spi-max-frequency = <19200000>;

		qcom,gpio-mosi = <&msmgpio 0  0>;
		qcom,gpio-miso = <&msmgpio 1  0>;
		qcom,gpio-clk  = <&msmgpio 3  0>;
		qcom,gpio-cs2  = <&msmgpio 11 0>;

		qcom,infinite-mode = <0>;
		qcom,use-bam;
		qcom,ver-reg-exists;
		qcom,bam-consumer-pipe-index = <12>;
		qcom,bam-producer-pipe-index = <13>;
		qcom,master-id = <86>;

		ethernet-switch@2 {
			compatible = "simtec,ks8851";
+5 −4
Original line number Diff line number Diff line
@@ -1075,16 +1075,17 @@
		interrupts = <0 95 0>, <0 238 0>;
		spi-max-frequency = <19200000>;

		gpios = <&msmgpio 3 0>, /* CLK  */
			<&msmgpio 1 0>, /* MISO */
			<&msmgpio 0 0>; /* MOSI */
		cs-gpios = <&msmgpio 22 0>;
		qcom,gpio-mosi = <&msmgpio 0 0>;
		qcom,gpio-miso = <&msmgpio 1 0>;
		qcom,gpio-clk  = <&msmgpio 3 0>;
		qcom,gpio-cs0  = <&msmgpio 22 0>;

		qcom,infinite-mode = <0>;
		qcom,use-bam;
		qcom,ver-reg-exists;
		qcom,bam-consumer-pipe-index = <12>;
		qcom,bam-producer-pipe-index = <13>;
		qcom,master-id = <86>;
	};

	qcom,bam_dmux@fc834000 {
+5 −4
Original line number Diff line number Diff line
@@ -521,16 +521,17 @@
		interrupts = <0 98 0>, <0 238 0>;
		spi-max-frequency = <50000000>;

		gpios = <&msmgpio 89 0>, /* CLK  */
			<&msmgpio 87 0>, /* MISO */
			<&msmgpio 86 0>; /* MOSI */
		cs-gpios = <&msmgpio 88 0>;
		qcom,gpio-mosi = <&msmgpio 86 0>;
		qcom,gpio-miso = <&msmgpio 87 0>;
		qcom,gpio-clk  = <&msmgpio 89 0>;
		qcom,gpio-cs0  = <&msmgpio 88 0>;

		qcom,infinite-mode = <0>;
		qcom,use-bam;
		qcom,ver-reg-exists;
		qcom,bam-consumer-pipe-index = <18>;
		qcom,bam-producer-pipe-index = <19>;
		qcom,master-id = <86>;
	};

	qcom,pronto@fb21b000 {
+25 −8
Original line number Diff line number Diff line
@@ -13,6 +13,12 @@
/include/ "msm8974-leds.dtsi"
/include/ "msm8974-camera-sensor-cdp.dtsi"

/ {
	aliases {
		spi0 = &spi_0;
	};
};

&soc {
	timer {
		clock-frequency = <5000000>;
@@ -42,17 +48,28 @@
		status = "disable";
	};

	spi@f9923000 {
	spi_0: spi@f9923000 { /* BLSP1 QUP1 */
		compatible = "qcom,spi-qup-v2";
		reg = <0xf9923000 0x1000>;
		interrupts = <0 95 0>;
		spi-max-frequency = <24000000>;
		#address-cells = <1>;
		#size-cells = <0>;
		gpios = <&msmgpio 3 0>, /* CLK  */
			<&msmgpio 1 0>, /* MISO */
			<&msmgpio 0 0>; /* MOSI */
		cs-gpios = <&msmgpio 9 0>;
		reg-names = "spi_physical", "spi_bam_physical";
		reg = <0xf9923000 0x1000>,
		      <0xf9904000 0xf000>;
		interrupt-names = "spi_irq", "spi_bam_irq";
		interrupts = <0 95 0>, <0 238 0>;
		spi-max-frequency = <19200000>;

		qcom,gpio-mosi = <&msmgpio 0 0>;
		qcom,gpio-miso = <&msmgpio 1 0>;
		qcom,gpio-clk  = <&msmgpio 3 0>;
		qcom,gpio-cs0  = <&msmgpio 9 0>;

		qcom,infinite-mode = <0>;
		qcom,use-bam;
		qcom,ver-reg-exists;
		qcom,bam-consumer-pipe-index = <12>;
		qcom,bam-producer-pipe-index = <13>;
		qcom,master-id = <86>;

		ethernet-switch@2 {
			compatible = "simtec,ks8851";
+31 −11
Original line number Diff line number Diff line
@@ -583,18 +583,28 @@
		qcom,bam-dma-res-pipes = <6>;
	};

	spi_7: spi_epm: spi@f9966000 {
	spi_7: spi_epm: spi@f9966000 { /* BLSP2 QUP4 */
		compatible = "qcom,spi-qup-v2";
		reg = <0xf9966000 0x1000>;
		interrupts = <0 104 0>;
		spi-max-frequency = <19200000>;
		#address-cells = <1>;
		#size-cells = <0>;
		qcom,master-id = <84>;
		reg-names = "spi_physical", "spi_bam_physical";
		reg = <0xf9966000 0x1000>,
		      <0xf9944000 0x15000>;
		interrupt-names = "spi_irq", "spi_bam_irq";
		interrupts = <0 104 0>, <0 239 0>;
		spi-max-frequency = <19200000>;

		qcom,gpio-mosi = <&msmgpio 53 0>;
		qcom,gpio-miso = <&msmgpio 54 0>;
		qcom,gpio-clk  = <&msmgpio 56 0>;
		qcom,gpio-cs0  = <&msmgpio 55 0>;

		qcom,infinite-mode = <0>;
		qcom,use-bam;
		qcom,ver-reg-exists;
		qcom,bam-consumer-pipe-index = <18>;
		qcom,bam-producer-pipe-index = <19>;
		qcom,master-id = <84>;
	};

	tspp: msm_tspp@f99d8000 {
@@ -819,18 +829,28 @@
		qcom,master-id = <86>;
	};

	spi_0: spi@f9923000 {
	spi_0: spi@f9923000 { /* BLSP1 QUP1 */
		compatible = "qcom,spi-qup-v2";
		reg = <0xf9923000 0x1000>;
		interrupts = <0 95 0>;
		spi-max-frequency = <19200000>;
		#address-cells = <1>;
		#size-cells = <0>;
		qcom,master-id = <86>;
		reg-names = "spi_physical", "spi_bam_physical";
		reg = <0xf9923000 0x1000>,
		      <0xf9904000 0xf000>;
		interrupt-names = "spi_irq", "spi_bam_irq";
		interrupts = <0 95 0>, <0 238 0>;
		spi-max-frequency = <19200000>;

		qcom,gpio-mosi = <&msmgpio 0 0>;
		qcom,gpio-miso = <&msmgpio 1 0>;
		qcom,gpio-clk  = <&msmgpio 3 0>;
		qcom,gpio-cs2  = <&msmgpio 9 0>;
		qcom,gpio-cs0  = <&msmgpio 9 0>;

		qcom,infinite-mode = <0>;
		qcom,use-bam;
		qcom,ver-reg-exists;
		qcom,bam-consumer-pipe-index = <12>;
		qcom,bam-producer-pipe-index = <13>;
		qcom,master-id = <86>;
	};

	qcom,acpuclk@f9000000 {
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