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Commit 92577e1c authored by Murali Nalajala's avatar Murali Nalajala
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msm: idle-v7: flush non secure L1 cache lines for l2 GDHS LPM mode 



It is LPM driver(HLOS) responsiblity to flush non secure lines of
L1 cache when the core decide to enter a LPM mode where core get
powered off. But current code is not flushing the non secure lines
of L1 cache when the core decide to enter into L2 GDHS LPM mode.
This change addresses the flushing of non secure lines of L1 cache.

CRs-fixed: 555905
Change-Id: I721947386091875994bcb71bd8b9b9b793a72349
Signed-off-by: default avatarMurali Nalajala <mnalajal@codeaurora.org>
parent 01364e16

arch/arm/mach-msm/idle-v7.S

+1 −0
Original line number Diff line number Diff line
@@ -200,6 +200,7 @@ THUMB( str r14, [r0],#4 ) 
	mov	r2, #1

	and	r1, r2, r1, ASR #30 /* Check if the cache is write back */

	orr	r1, r0, r1

	and	r1, r1, #1

	cmp	r1, #1

	bne	skip

	bl	v7_flush_dcache_all