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Commit 90804c3b authored by Jack Pham's avatar Jack Pham
Browse files

usb: dwc3-msm: Switch master clock rate to XO when disabling 



After the USB driver disables its clocks, such as during cable
disconnect, when the system enters XO shutdown, the USB30
master clock may experience clock glitches when its PLL is
forcibly shut off. To avoid this, switch the USB30 master
clock rate to XO (19.2 MHz) just before disabling it.

Change-Id: I1951a7877ce7b4c8cb86577f5ba921fd17a6ad63
Signed-off-by: default avatarJack Pham <jackp@codeaurora.org>
parent 4c8a1573

drivers/usb/dwc3/dwc3-msm.c

+4 −0
Original line number Diff line number Diff line
@@ -1713,6 +1713,7 @@ static int dwc3_msm_suspend(struct dwc3_msm *mdwc) 
	clk_disable_unprepare(mdwc->utmi_clk);



	if (can_suspend_ssphy) {

		clk_set_rate(mdwc->core_clk, 19200000);

		clk_disable_unprepare(mdwc->core_clk);

		mdwc->lpm_flags |= MDWC3_CORECLK_OFF;

		/* USB PHY no more requires TCXO */
@@ -1829,6 +1830,7 @@ static int dwc3_msm_resume(struct dwc3_msm *mdwc) 


	clk_prepare_enable(mdwc->iface_clk);

	if (mdwc->lpm_flags & MDWC3_CORECLK_OFF) {

		clk_set_rate(mdwc->core_clk, 125000000);

		clk_prepare_enable(mdwc->core_clk);

		mdwc->lpm_flags &= ~MDWC3_CORECLK_OFF;

	}
@@ -3258,6 +3260,7 @@ disable_sleep_clk: 
disable_iface_clk:

	clk_disable_unprepare(mdwc->iface_clk);

disable_core_clk:

	clk_set_rate(mdwc->core_clk, 19200000);

	clk_disable_unprepare(mdwc->core_clk);

disable_xo:

	clk_disable_unprepare(mdwc->xo_clk);
@@ -3337,6 +3340,7 @@ static int dwc3_msm_remove(struct platform_device *pdev) 
		disable_irq(mdwc->pwr_event_irq);



	clk_disable_unprepare(mdwc->utmi_clk);

	clk_set_rate(mdwc->core_clk, 19200000);

	clk_disable_unprepare(mdwc->core_clk);

	clk_disable_unprepare(mdwc->iface_clk);

	clk_disable_unprepare(mdwc->sleep_clk);