Loading arch/arm/boot/dts/qcom/msmplutonium-coresight.dtsi +23 −0 Original line number Diff line number Diff line Loading @@ -679,4 +679,27 @@ <&clock_rpm clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; }; hwevent: hwevent@fd820018 { compatible = "qcom,coresight-hwevent"; reg = <0xfd828018 0x80>, <0xf9112000 0x80>, <0xfd4ab160 0x80>, <0xfc401600 0x80>, <0xfd4ab360 0x80>, <0xfc596000 0x80>, <0xfc520058 0x80>, <0xfc528058 0x80>; reg-names = "mmss-mux", "apcs-mux", "ppss-mux", "gcc-mux", "tcsr-mux", "ufs-mux", "pcie0-mux", "pcie1-mux" ; coresight-id = <44>; coresight-name = "coresight-hwevent"; coresight-nr-inports = <0>; clocks = <&clock_rpm clk_qdss_clk>, <&clock_rpm clk_qdss_a_clk>, <&clock_mmss clk_mmss_misc_ahb_clk>; clock-names = "core_clk", "core_a_clk", "core_mmss_clk"; }; }; Loading
arch/arm/boot/dts/qcom/msmplutonium-coresight.dtsi +23 −0 Original line number Diff line number Diff line Loading @@ -679,4 +679,27 @@ <&clock_rpm clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; }; hwevent: hwevent@fd820018 { compatible = "qcom,coresight-hwevent"; reg = <0xfd828018 0x80>, <0xf9112000 0x80>, <0xfd4ab160 0x80>, <0xfc401600 0x80>, <0xfd4ab360 0x80>, <0xfc596000 0x80>, <0xfc520058 0x80>, <0xfc528058 0x80>; reg-names = "mmss-mux", "apcs-mux", "ppss-mux", "gcc-mux", "tcsr-mux", "ufs-mux", "pcie0-mux", "pcie1-mux" ; coresight-id = <44>; coresight-name = "coresight-hwevent"; coresight-nr-inports = <0>; clocks = <&clock_rpm clk_qdss_clk>, <&clock_rpm clk_qdss_a_clk>, <&clock_mmss clk_mmss_misc_ahb_clk>; clock-names = "core_clk", "core_a_clk", "core_mmss_clk"; }; };