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Commit 8d5e1bfa authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Add soft reset for A4XX"

parents 0d6eafbe b27a57db

drivers/gpu/msm/a4xx_reg.h

+2 −0
Original line number Diff line number Diff line
@@ -35,6 +35,8 @@ enum a4xx_rb_perfctr_rb_sel { 
/* RBBM registers */

#define A4XX_RBBM_AHB_CMD		0x25

#define A4XX_RBBM_SP_HYST_CNT		0x21

#define A4XX_RBBM_SW_RESET_CMD		0x22



#define A4XX_RBBM_AHB_CTL0		0x23

#define A4XX_RBBM_AHB_CTL1		0x24

#define A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL	0x2b

drivers/gpu/msm/adreno.h

+1 −0
Original line number Diff line number Diff line
@@ -311,6 +311,7 @@ enum adreno_regs { 
	ADRENO_REG_RBBM_PM_OVERRIDE2,

	ADRENO_REG_RBBM_AHB_CMD,

	ADRENO_REG_RBBM_INT_CLEAR_CMD,

	ADRENO_REG_RBBM_SW_RESET_CMD,

	ADRENO_REG_VPC_DEBUG_RAM_SEL,

	ADRENO_REG_VPC_DEBUG_RAM_READ,

	ADRENO_REG_VSC_PIPE_DATA_ADDRESS_0,

drivers/gpu/msm/adreno_a3xx.c

+5 −5
Original line number Diff line number Diff line
@@ -4196,18 +4196,17 @@ void a3xx_coresight_config_debug_reg(struct kgsl_device *device, 
 * all the HW logic, restores GPU registers to default state and

 * flushes out pending VBIF transactions.

 */

static void a3xx_soft_reset(struct adreno_device *adreno_dev)

void a3xx_soft_reset(struct adreno_device *adreno_dev)

{

	struct kgsl_device *device = &adreno_dev->dev;

	unsigned int reg;



	kgsl_regwrite(device, A3XX_RBBM_SW_RESET_CMD, 1);

	adreno_writereg(adreno_dev, ADRENO_REG_RBBM_SW_RESET_CMD, 1);

	/*

	 * Do a dummy read to get a brief read cycle delay for the reset to take

	 * effect

	 */

	kgsl_regread(device, A3XX_RBBM_SW_RESET_CMD, &reg);

	kgsl_regwrite(device, A3XX_RBBM_SW_RESET_CMD, 0);

	adreno_readreg(adreno_dev, ADRENO_REG_RBBM_SW_RESET_CMD, &reg);

	adreno_writereg(adreno_dev, ADRENO_REG_RBBM_SW_RESET_CMD, 0);

}



/* Defined in adreno_a3xx_snapshot.c */
@@ -4437,6 +4436,7 @@ static unsigned int a3xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
	ADRENO_REG_DEFINE(ADRENO_REG_TC_CNTL_STATUS, REG_TC_CNTL_STATUS),

	ADRENO_REG_DEFINE(ADRENO_REG_TP0_CHICKEN, REG_TP0_CHICKEN),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_RBBM_CTL, A3XX_RBBM_RBBM_CTL),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SW_RESET_CMD, A3XX_RBBM_SW_RESET_CMD),

};



const struct adreno_reg_offsets a3xx_reg_offsets = {

drivers/gpu/msm/adreno_a3xx.h

+1 −1
Original line number Diff line number Diff line
@@ -27,5 +27,5 @@ uint64_t a3xx_perfcounter_read(struct adreno_device *adreno_dev, 
	unsigned int group, unsigned int counter);

void a3xx_perfcounter_disable(struct adreno_device *adreno_dev,

	unsigned int group, unsigned int counter);



void a3xx_soft_reset(struct adreno_device *adreno_dev);

#endif /*__A3XX_H */

drivers/gpu/msm/adreno_a4xx.c

+2 −0
Original line number Diff line number Diff line
@@ -321,6 +321,7 @@ static unsigned int a4xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
	ADRENO_REG_DEFINE(ADRENO_REG_SP_FS_OBJ_START_REG,

				A4XX_SP_FS_OBJ_START),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_RBBM_CTL, A4XX_RBBM_RBBM_CTL),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SW_RESET_CMD, A4XX_RBBM_SW_RESET_CMD),

};



const struct adreno_reg_offsets a4xx_reg_offsets = {
@@ -663,4 +664,5 @@ struct adreno_gpudev adreno_a4xx_gpudev = { 
	.perfcounter_enable = a3xx_perfcounter_enable,

	.perfcounter_read = a3xx_perfcounter_read,

	.invalid_countables = a4xx_perfctr_invalid_countables,

	.soft_reset = a3xx_soft_reset,

};