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Commit 8b827c60 authored by Gregory CLEMENT's avatar Gregory CLEMENT Committed by Russell King
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ARM: 7615/1: cache-l2x0: aurora: Invalidate during clean operation with WT enable 



This patch fixes a bug for Aurora L2 cache controller when the
write-through mode is enable. For the clean operation even if we don't
have to flush the lines we still need to invalidate them.

Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: default avatarJason Cooper <jason@lakedaemon.net>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent d106de38

arch/arm/mm/cache-l2x0.c

+14 −8
Original line number Diff line number Diff line
@@ -506,17 +506,23 @@ static void aurora_clean_range(unsigned long start, unsigned long end) 


static void aurora_flush_range(unsigned long start, unsigned long end)

{

	if (!l2_wt_override) {

	start &= ~(CACHE_LINE_SIZE - 1);

	end = ALIGN(end, CACHE_LINE_SIZE);

	while (start != end) {

		unsigned long range_end = calc_range_end(start, end);

		/*

		 * If L2 is forced to WT, the L2 will always be clean and we

		 * just need to invalidate.

		 */

		if (l2_wt_override)

			aurora_pa_range(start, range_end - CACHE_LINE_SIZE,

							AURORA_INVAL_RANGE_REG);

		else

			aurora_pa_range(start, range_end - CACHE_LINE_SIZE,

							AURORA_FLUSH_RANGE_REG);

		start = range_end;

	}

}

}



static void __init l2x0_of_setup(const struct device_node *np,

				 u32 *aux_val, u32 *aux_mask)