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Commit 8aa75009 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: cayman/evergreen cs checker updates 



Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 9b91d18d

drivers/gpu/drm/radeon/evergreen_cs.c

+18 −2
Original line number Original line Diff line number Diff line
@@ -479,8 +479,24 @@ static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u3 
	case SQ_VSTMP_RING_ITEMSIZE:

	case SQ_VSTMP_RING_ITEMSIZE:

	case VGT_TF_RING_SIZE:

	case VGT_TF_RING_SIZE:

		/* get value to populate the IB don't remove */

		/* get value to populate the IB don't remove */

		tmp =radeon_get_ib_value(p, idx);

		/*tmp =radeon_get_ib_value(p, idx);

		ib[idx] = 0;

		  ib[idx] = 0;*/

		break;

	case SQ_ESGS_RING_BASE:

	case SQ_GSVS_RING_BASE:

	case SQ_ESTMP_RING_BASE:

	case SQ_GSTMP_RING_BASE:

	case SQ_HSTMP_RING_BASE:

	case SQ_LSTMP_RING_BASE:

	case SQ_PSTMP_RING_BASE:

	case SQ_VSTMP_RING_BASE:

		r = evergreen_cs_packet_next_reloc(p, &reloc);

		if (r) {

			dev_warn(p->dev, "bad SET_CONTEXT_REG "

					"0x%04X\n", reg);

			return -EINVAL;

		}

		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);

		break;

		break;

	case DB_DEPTH_CONTROL:

	case DB_DEPTH_CONTROL:

		track->db_depth_control = radeon_get_ib_value(p, idx);

		track->db_depth_control = radeon_get_ib_value(p, idx);

drivers/gpu/drm/radeon/evergreend.h

+8 −0
Original line number Original line Diff line number Diff line
@@ -754,13 +754,21 @@ 




#define SQ_CONST_MEM_BASE				0x8df8

#define SQ_CONST_MEM_BASE				0x8df8





#define SQ_ESGS_RING_BASE				0x8c40

#define SQ_ESGS_RING_SIZE				0x8c44

#define SQ_ESGS_RING_SIZE				0x8c44

#define SQ_GSVS_RING_BASE				0x8c48

#define SQ_GSVS_RING_SIZE				0x8c4c

#define SQ_GSVS_RING_SIZE				0x8c4c

#define SQ_ESTMP_RING_BASE				0x8c50

#define SQ_ESTMP_RING_SIZE				0x8c54

#define SQ_ESTMP_RING_SIZE				0x8c54

#define SQ_GSTMP_RING_BASE				0x8c58

#define SQ_GSTMP_RING_SIZE				0x8c5c

#define SQ_GSTMP_RING_SIZE				0x8c5c

#define SQ_VSTMP_RING_BASE				0x8c60

#define SQ_VSTMP_RING_SIZE				0x8c64

#define SQ_VSTMP_RING_SIZE				0x8c64

#define SQ_PSTMP_RING_BASE				0x8c68

#define SQ_PSTMP_RING_SIZE				0x8c6c

#define SQ_PSTMP_RING_SIZE				0x8c6c

#define SQ_LSTMP_RING_BASE				0x8e10

#define SQ_LSTMP_RING_SIZE				0x8e14

#define SQ_LSTMP_RING_SIZE				0x8e14

#define SQ_HSTMP_RING_BASE				0x8e18

#define SQ_HSTMP_RING_SIZE				0x8e1c

#define SQ_HSTMP_RING_SIZE				0x8e1c

#define VGT_TF_RING_SIZE				0x8988

#define VGT_TF_RING_SIZE				0x8988

drivers/gpu/drm/radeon/reg_srcs/cayman

+2 −0
Original line number Original line Diff line number Diff line 
cayman 0x9400

cayman 0x9400

0x0000802C GRBM_GFX_INDEX

0x000088B0 VGT_VTX_VECT_EJECT_REG

0x000088B0 VGT_VTX_VECT_EJECT_REG

0x000088C4 VGT_CACHE_INVALIDATION

0x000088C4 VGT_CACHE_INVALIDATION

0x000088D4 VGT_GS_VERTEX_REUSE

0x000088D4 VGT_GS_VERTEX_REUSE
@@ -205,6 +206,7 @@ cayman 0x9400 
0x00028348 PA_SC_VPORT_ZMIN_15

0x00028348 PA_SC_VPORT_ZMIN_15

0x0002834C PA_SC_VPORT_ZMAX_15

0x0002834C PA_SC_VPORT_ZMAX_15

0x00028350 SX_MISC

0x00028350 SX_MISC

0x00028354 SX_SURFACE_SYNC

0x00028380 SQ_VTX_SEMANTIC_0

0x00028380 SQ_VTX_SEMANTIC_0

0x00028384 SQ_VTX_SEMANTIC_1

0x00028384 SQ_VTX_SEMANTIC_1

0x00028388 SQ_VTX_SEMANTIC_2

0x00028388 SQ_VTX_SEMANTIC_2

drivers/gpu/drm/radeon/reg_srcs/evergreen

+2 −0
Original line number Original line Diff line number Diff line 
evergreen 0x9400

evergreen 0x9400

0x0000802C GRBM_GFX_INDEX

0x00008040 WAIT_UNTIL

0x00008040 WAIT_UNTIL

0x00008044 WAIT_UNTIL_POLL_CNTL

0x00008044 WAIT_UNTIL_POLL_CNTL

0x00008048 WAIT_UNTIL_POLL_MASK

0x00008048 WAIT_UNTIL_POLL_MASK
@@ -220,6 +221,7 @@ evergreen 0x9400 
0x00028348 PA_SC_VPORT_ZMIN_15

0x00028348 PA_SC_VPORT_ZMIN_15

0x0002834C PA_SC_VPORT_ZMAX_15

0x0002834C PA_SC_VPORT_ZMAX_15

0x00028350 SX_MISC

0x00028350 SX_MISC

0x00028354 SX_SURFACE_SYNC

0x00028380 SQ_VTX_SEMANTIC_0

0x00028380 SQ_VTX_SEMANTIC_0

0x00028384 SQ_VTX_SEMANTIC_1

0x00028384 SQ_VTX_SEMANTIC_1

0x00028388 SQ_VTX_SEMANTIC_2

0x00028388 SQ_VTX_SEMANTIC_2