Loading drivers/gpu/msm/adreno_a3xx.c +11 −9 Original line number Diff line number Diff line Loading @@ -35,14 +35,14 @@ const unsigned int a3xx_registers[] = { /* RBBM REGISTERS */ 0x0000, 0x0002, 0x0010, 0x0012, 0x0018, 0x0018, 0x0020, 0x0027, 0x0029, 0x002b, 0x002e, 0x0033, 0x0040, 0x0042, 0x0050, 0x005c, 0x0029, 0x002b, 0x002d, 0x0033, 0x0040, 0x0042, 0x0050, 0x005c, 0x0060, 0x006c, 0x0080, 0x0082, 0x0084, 0x0088, 0x0090, 0x00e5, 0x00ea, 0x00ed, 0x0100, 0x0100, 0x0110, 0x0123, /* CP REGISTERS */ 0x01c0, 0x01c1, 0x01c3, 0x01c5, 0x01c7, 0x01c7, 0x01d5, 0x01d9, 0x01dc, 0x01dd, 0x01ea, 0x01ea, 0x01ee, 0x01f1, 0x01f5, 0x01f5, 0x01fc, 0x01ff, 0x0440, 0x0440, 0x0443, 0x0443, 0x0445, 0x0445, 0x044d, 0x044f, 0x0452, 0x0452, 0x0454, 0x046f, 0x047c, 0x047c, 0x01c0, 0x01c1, 0x01c3, 0x01c5, 0x01c7, 0x01c7, 0x01c9, 0x01ca, 0x01cc, 0x01cd, 0x01d4, 0x01dd, 0x01ea, 0x01ea, 0x01ec, 0x01f1, 0x01f5, 0x01fa, 0x01fc, 0x01ff, 0x0440, 0x0440, 0x0443, 0x0443, 0x0445, 0x0445, 0x044d, 0x044f, 0x0452, 0x046f, 0x047c, 0x047c, 0x047f, 0x047f, 0x0578, 0x057f, 0x0600, 0x0602, 0x0605, 0x0607, 0x060a, 0x060e, 0x0612, 0x0614, /* VSC REGISTERS */ Loading @@ -50,11 +50,13 @@ const unsigned int a3xx_registers[] = { /* PC REGISTERS */ 0x0c3d, 0x0c3f, 0x0c48, 0x0c4b, /* GRAS REGISTERS */ 0x0c80, 0x0c80, 0x0c88, 0x0c8b, 0x0ca0, 0x0cb7, 0x0c80, 0x0c81, 0x0c88, 0x0c8b, 0x0ca0, 0x0cb7, /* RB REGISTERS */ 0x0cc0, 0x0cc1, 0x0cc6, 0x0cc7, /* MARB REGISTERS */ 0x0ce4, 0x0ce5, /* VSC REGISTERS */ 0x0d00, 0x0d01, 0x0d24, 0x0d33, /* VFD REGISTERS*/ 0x0e41, 0x0e45, /* VPC REGISTERS */ Loading @@ -62,12 +64,12 @@ const unsigned int a3xx_registers[] = { /* UCHE REGISTERS */ 0x0e80, 0x0e82, 0x0e84, 0x0e89, 0x0ea0, 0x0ea1, 0x0ea4, 0x0ea7, /* SP REGISTERS */ 0x0ec4, 0x0ecb, 0x0ee0, 0x0ee0, 0x0ec0, 0x0ec2, 0x0ec4, 0x0ecb, 0x0ee0, 0x0ee0, /* TPL1 REGISTERS */ 0x0f00, 0x0f01, 0x0f03, 0x0f09, /* GRAS CTX 0 */ 0x2040, 0x2040, 0x2044, 0x2044, 0x2048, 0x204d, 0x2068, 0x2069, 0x206c, 0x206d, 0x2070, 0x2070, 0x2072, 0x2072, 0x2074, 0x2075, 0x206c, 0x206f, 0x2070, 0x2070, 0x2072, 0x2072, 0x2074, 0x2075, 0x2079, 0x207a, /* RB CTX 0 */ 0x20c0, 0x20d3, 0x20e4, 0x20ef, 0x2100, 0x2109, 0x210c, 0x210c, Loading @@ -85,7 +87,7 @@ const unsigned int a3xx_registers[] = { 0x2340, 0x2343, /* GRAS CTX 1 */ 0x2440, 0x2440, 0x2444, 0x2444, 0x2448, 0x244d, 0x2468, 0x2469, 0x246c, 0x246d, 0x2470, 0x2470, 0x2472, 0x2472, 0x2474, 0x2475, 0x246c, 0x246f, 0x2470, 0x2470, 0x2472, 0x2472, 0x2474, 0x2475, 0x2479, 0x247a, /* RB CTX 1 */ 0x24c0, 0x24d3, 0x24e4, 0x24ef, 0x2500, 0x2509, 0x250c, 0x250c, Loading Loading
drivers/gpu/msm/adreno_a3xx.c +11 −9 Original line number Diff line number Diff line Loading @@ -35,14 +35,14 @@ const unsigned int a3xx_registers[] = { /* RBBM REGISTERS */ 0x0000, 0x0002, 0x0010, 0x0012, 0x0018, 0x0018, 0x0020, 0x0027, 0x0029, 0x002b, 0x002e, 0x0033, 0x0040, 0x0042, 0x0050, 0x005c, 0x0029, 0x002b, 0x002d, 0x0033, 0x0040, 0x0042, 0x0050, 0x005c, 0x0060, 0x006c, 0x0080, 0x0082, 0x0084, 0x0088, 0x0090, 0x00e5, 0x00ea, 0x00ed, 0x0100, 0x0100, 0x0110, 0x0123, /* CP REGISTERS */ 0x01c0, 0x01c1, 0x01c3, 0x01c5, 0x01c7, 0x01c7, 0x01d5, 0x01d9, 0x01dc, 0x01dd, 0x01ea, 0x01ea, 0x01ee, 0x01f1, 0x01f5, 0x01f5, 0x01fc, 0x01ff, 0x0440, 0x0440, 0x0443, 0x0443, 0x0445, 0x0445, 0x044d, 0x044f, 0x0452, 0x0452, 0x0454, 0x046f, 0x047c, 0x047c, 0x01c0, 0x01c1, 0x01c3, 0x01c5, 0x01c7, 0x01c7, 0x01c9, 0x01ca, 0x01cc, 0x01cd, 0x01d4, 0x01dd, 0x01ea, 0x01ea, 0x01ec, 0x01f1, 0x01f5, 0x01fa, 0x01fc, 0x01ff, 0x0440, 0x0440, 0x0443, 0x0443, 0x0445, 0x0445, 0x044d, 0x044f, 0x0452, 0x046f, 0x047c, 0x047c, 0x047f, 0x047f, 0x0578, 0x057f, 0x0600, 0x0602, 0x0605, 0x0607, 0x060a, 0x060e, 0x0612, 0x0614, /* VSC REGISTERS */ Loading @@ -50,11 +50,13 @@ const unsigned int a3xx_registers[] = { /* PC REGISTERS */ 0x0c3d, 0x0c3f, 0x0c48, 0x0c4b, /* GRAS REGISTERS */ 0x0c80, 0x0c80, 0x0c88, 0x0c8b, 0x0ca0, 0x0cb7, 0x0c80, 0x0c81, 0x0c88, 0x0c8b, 0x0ca0, 0x0cb7, /* RB REGISTERS */ 0x0cc0, 0x0cc1, 0x0cc6, 0x0cc7, /* MARB REGISTERS */ 0x0ce4, 0x0ce5, /* VSC REGISTERS */ 0x0d00, 0x0d01, 0x0d24, 0x0d33, /* VFD REGISTERS*/ 0x0e41, 0x0e45, /* VPC REGISTERS */ Loading @@ -62,12 +64,12 @@ const unsigned int a3xx_registers[] = { /* UCHE REGISTERS */ 0x0e80, 0x0e82, 0x0e84, 0x0e89, 0x0ea0, 0x0ea1, 0x0ea4, 0x0ea7, /* SP REGISTERS */ 0x0ec4, 0x0ecb, 0x0ee0, 0x0ee0, 0x0ec0, 0x0ec2, 0x0ec4, 0x0ecb, 0x0ee0, 0x0ee0, /* TPL1 REGISTERS */ 0x0f00, 0x0f01, 0x0f03, 0x0f09, /* GRAS CTX 0 */ 0x2040, 0x2040, 0x2044, 0x2044, 0x2048, 0x204d, 0x2068, 0x2069, 0x206c, 0x206d, 0x2070, 0x2070, 0x2072, 0x2072, 0x2074, 0x2075, 0x206c, 0x206f, 0x2070, 0x2070, 0x2072, 0x2072, 0x2074, 0x2075, 0x2079, 0x207a, /* RB CTX 0 */ 0x20c0, 0x20d3, 0x20e4, 0x20ef, 0x2100, 0x2109, 0x210c, 0x210c, Loading @@ -85,7 +87,7 @@ const unsigned int a3xx_registers[] = { 0x2340, 0x2343, /* GRAS CTX 1 */ 0x2440, 0x2440, 0x2444, 0x2444, 0x2448, 0x244d, 0x2468, 0x2469, 0x246c, 0x246d, 0x2470, 0x2470, 0x2472, 0x2472, 0x2474, 0x2475, 0x246c, 0x246f, 0x2470, 0x2470, 0x2472, 0x2472, 0x2474, 0x2475, 0x2479, 0x247a, /* RB CTX 1 */ 0x24c0, 0x24d3, 0x24e4, 0x24ef, 0x2500, 0x2509, 0x250c, 0x250c, Loading