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Commit 873b4709 authored by Matt Wagantall's avatar Matt Wagantall Committed by Stephen Boyd
Browse files

msm: acpuclock-krait: Discard unused SoC-specific data by using __initdata 



Refactor the initialization code so that datastructures that must be
kept are kmemduped and the rest are discarded after the kernel has
booted with the help of __initdata markings.

For a typically-compiled all-in-one kernel containing support for
msm8960, apq8064, msm8627 and msm8930, this allows 11.5K to be moved
from the .data to the .init.data section, with less than 10% of that
retained in dynamically-allocated memory (the exact amount varies
depending on the device the kernel is booted on).

Change-Id: I505eef8f10dc0e44bab15954b797252c3c408e50
Signed-off-by: default avatarMatt Wagantall <mattw@codeaurora.org>
parent c2764de6

arch/arm/mach-msm/acpuclock-8064.c

+22 −21
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ 
#include "acpuclock.h"

#include "acpuclock-krait.h"



static struct hfpll_data hfpll_data = {

static struct hfpll_data hfpll_data __initdata = {

	.mode_offset = 0x00,

	.l_offset = 0x08,

	.m_offset = 0x0C,
@@ -37,10 +37,9 @@ static struct hfpll_data hfpll_data = { 
	.vdd[HFPLL_VDD_NOM]  = 1050000,

};



static struct scalable scalable[] = {

static struct scalable scalable[] __initdata = {

	[CPU0] = {

		.hfpll_phys_base = 0x00903200,

		.hfpll_data = &hfpll_data,

		.aux_clk_sel_phys = 0x02088014,

		.aux_clk_sel = 3,

		.l2cpmr_iaddr = 0x4501,
@@ -51,7 +50,6 @@ static struct scalable scalable[] = { 
	},

	[CPU1] = {

		.hfpll_phys_base = 0x00903240,

		.hfpll_data = &hfpll_data,

		.aux_clk_sel_phys = 0x02098014,

		.aux_clk_sel = 3,

		.l2cpmr_iaddr = 0x5501,
@@ -62,7 +60,6 @@ static struct scalable scalable[] = { 
	},

	[CPU2] = {

		.hfpll_phys_base = 0x00903280,

		.hfpll_data = &hfpll_data,

		.aux_clk_sel_phys = 0x020A8014,

		.aux_clk_sel = 3,

		.l2cpmr_iaddr = 0x6501,
@@ -73,7 +70,6 @@ static struct scalable scalable[] = { 
	},

	[CPU3] = {

		.hfpll_phys_base = 0x009032C0,

		.hfpll_data = &hfpll_data,

		.aux_clk_sel_phys = 0x020B8014,

		.aux_clk_sel = 3,

		.l2cpmr_iaddr = 0x7501,
@@ -84,7 +80,6 @@ static struct scalable scalable[] = { 
	},

	[L2] = {

		.hfpll_phys_base = 0x00903300,

		.hfpll_data = &hfpll_data,

		.aux_clk_sel_phys = 0x02011028,

		.aux_clk_sel = 3,

		.l2cpmr_iaddr = 0x0500,
@@ -92,7 +87,7 @@ static struct scalable scalable[] = { 
	},

};



static struct msm_bus_paths bw_level_tbl[] = {

static struct msm_bus_paths bw_level_tbl[] __initdata = {

	[0] =  BW_MBPS(640), /* At least  80 MHz on bus. */

	[1] = BW_MBPS(1064), /* At least 133 MHz on bus. */

	[2] = BW_MBPS(1600), /* At least 200 MHz on bus. */
@@ -101,14 +96,14 @@ static struct msm_bus_paths bw_level_tbl[] = { 
	[5] = BW_MBPS(4264), /* At least 533 MHz on bus. */

};



static struct msm_bus_scale_pdata bus_scale_data = {

static struct msm_bus_scale_pdata bus_scale_data __initdata = {

	.usecase = bw_level_tbl,

	.num_usecases = ARRAY_SIZE(bw_level_tbl),

	.active_only = 1,

	.name = "acpuclk-8064",

};



static struct l2_level l2_freq_tbl[] = {

static struct l2_level l2_freq_tbl[] __initdata __initdata = {

	[0]  = { {STBY_KHZ, QSB,   0, 0, 0x00 }, 1050000, 1050000, 0 },

	[1]  = { {  384000, PLL_8, 0, 2, 0x00 }, 1050000, 1050000, 1 },

	[2]  = { {  432000, HFPLL, 2, 0, 0x20 }, 1050000, 1050000, 2 },
@@ -127,7 +122,7 @@ static struct l2_level l2_freq_tbl[] = { 
	[15] = { { 1134000, HFPLL, 1, 0, 0x2A }, 1150000, 1150000, 5 },

};



static struct acpu_level acpu_freq_tbl_slow[] = {

static struct acpu_level acpu_freq_tbl_slow[] __initdata = {

	{ 0, { STBY_KHZ, QSB,   0, 0, 0x00 }, L2(0),   950000 },

	{ 1, {   384000, PLL_8, 0, 2, 0x00 }, L2(1),   950000 },

	{ 0, {   432000, HFPLL, 2, 0, 0x20 }, L2(7),   975000 },
@@ -154,7 +149,7 @@ static struct acpu_level acpu_freq_tbl_slow[] = { 
	{ 0, { 0 } }

};



static struct acpu_level acpu_freq_tbl_nom[] = {

static struct acpu_level acpu_freq_tbl_nom[] __initdata = {

	{ 0, { STBY_KHZ, QSB,   0, 0, 0x00 }, L2(0),   900000 },

	{ 1, {   384000, PLL_8, 0, 2, 0x00 }, L2(1),   900000 },

	{ 0, {   432000, HFPLL, 2, 0, 0x20 }, L2(7),   925000 },
@@ -181,7 +176,7 @@ static struct acpu_level acpu_freq_tbl_nom[] = { 
	{ 0, { 0 } }

};



static struct acpu_level acpu_freq_tbl_fast[] = {

static struct acpu_level acpu_freq_tbl_fast[] __initdata = {

	{ 0, { STBY_KHZ, QSB,   0, 0, 0x00 }, L2(0),   850000 },

	{ 1, {   384000, PLL_8, 0, 2, 0x00 }, L2(1),   850000 },

	{ 0, {   432000, HFPLL, 2, 0, 0x20 }, L2(7),   875000 },
@@ -208,16 +203,22 @@ static struct acpu_level acpu_freq_tbl_fast[] = { 
	{ 0, { 0 } }

};



static struct acpuclk_krait_params acpuclk_8064_params = {

	.scalable = scalable,

	.pvs_acpu_freq_tbl[PVS_SLOW] = acpu_freq_tbl_slow,

	.pvs_acpu_freq_tbl[PVS_NOMINAL] = acpu_freq_tbl_nom,

	.pvs_acpu_freq_tbl[PVS_FAST] = acpu_freq_tbl_fast,

static struct pvs_table pvs_tables[NUM_PVS] __initdata = {

	[PVS_SLOW]    = { acpu_freq_tbl_slow, sizeof(acpu_freq_tbl_slow) },

	[PVS_NOMINAL] = { acpu_freq_tbl_nom,  sizeof(acpu_freq_tbl_nom)  },

	[PVS_FAST]    = { acpu_freq_tbl_fast, sizeof(acpu_freq_tbl_fast) },

	/* TODO: update the faster table when data is available */

	.pvs_acpu_freq_tbl[PVS_FASTER] = acpu_freq_tbl_fast,

	[PVS_FASTER]  = { acpu_freq_tbl_fast, sizeof(acpu_freq_tbl_fast) },

};



static struct acpuclk_krait_params acpuclk_8064_params __initdata = {

	.scalable = scalable,

	.scalable_size = sizeof(scalable),

	.hfpll_data = &hfpll_data,

	.pvs_tables = pvs_tables,

	.l2_freq_tbl = l2_freq_tbl,

	.l2_freq_tbl_size = ARRAY_SIZE(l2_freq_tbl),

	.bus_scale_data = &bus_scale_data,

	.l2_freq_tbl_size = sizeof(l2_freq_tbl),

	.bus_scale = &bus_scale_data,

	.qfprom_phys_base = 0x00700000,

};

arch/arm/mach-msm/acpuclock-8627.c

+18 −15
Original line number Diff line number Diff line
@@ -27,7 +27,7 @@ 
#define LVL_NOM		RPM_VREG_CORNER_NOMINAL

#define LVL_HIGH	RPM_VREG_CORNER_HIGH



static struct hfpll_data hfpll_data = {

static struct hfpll_data hfpll_data __initdata = {

	.mode_offset = 0x00,

	.l_offset = 0x08,

	.m_offset = 0x0C,
@@ -43,10 +43,9 @@ static struct hfpll_data hfpll_data = { 
	.vdd[HFPLL_VDD_NOM]  = LVL_NOM,

};



static struct scalable scalable[] = {

static struct scalable scalable[] __initdata = {

	[CPU0] = {

		.hfpll_phys_base = 0x00903200,

		.hfpll_data = &hfpll_data,

		.aux_clk_sel_phys = 0x02088014,

		.aux_clk_sel = 3,

		.l2cpmr_iaddr = 0x4501,
@@ -57,7 +56,6 @@ static struct scalable scalable[] = { 
	},

	[CPU1] = {

		.hfpll_phys_base = 0x00903300,

		.hfpll_data = &hfpll_data,

		.aux_clk_sel_phys = 0x02098014,

		.aux_clk_sel = 3,

		.l2cpmr_iaddr = 0x5501,
@@ -68,7 +66,6 @@ static struct scalable scalable[] = { 
	},

	[L2] = {

		.hfpll_phys_base = 0x00903400,

		.hfpll_data = &hfpll_data,

		.aux_clk_sel_phys = 0x02011028,

		.aux_clk_sel = 3,

		.l2cpmr_iaddr = 0x0500,
@@ -76,7 +73,7 @@ static struct scalable scalable[] = { 
	},

};



static struct msm_bus_paths bw_level_tbl[] = {

static struct msm_bus_paths bw_level_tbl[] __initdata = {

	[0] =  BW_MBPS(640), /* At least  80 MHz on bus. */

	[1] = BW_MBPS(1064), /* At least 133 MHz on bus. */

	[2] = BW_MBPS(1600), /* At least 200 MHz on bus. */
@@ -84,7 +81,7 @@ static struct msm_bus_paths bw_level_tbl[] = { 
	[4] = BW_MBPS(3200), /* At least 400 MHz on bus. */

};



static struct msm_bus_scale_pdata bus_scale_data = {

static struct msm_bus_scale_pdata bus_scale_data __initdata = {

	.usecase = bw_level_tbl,

	.num_usecases = ARRAY_SIZE(bw_level_tbl),

	.active_only = 1,
@@ -92,7 +89,7 @@ static struct msm_bus_scale_pdata bus_scale_data = { 
};



/* TODO: Update vdd_dig, vdd_mem and bw when data is available. */

static struct l2_level l2_freq_tbl[] = {

static struct l2_level l2_freq_tbl[] __initdata = {

	[0]  = { {STBY_KHZ, QSB,   0, 0, 0x00 },  LVL_NOM, 1050000, 0 },

	[1]  = { {  384000, PLL_8, 0, 2, 0x00 },  LVL_NOM, 1050000, 1 },

	[2]  = { {  432000, HFPLL, 2, 0, 0x20 },  LVL_NOM, 1050000, 1 },
@@ -109,7 +106,7 @@ static struct l2_level l2_freq_tbl[] = { 
};



/* TODO: Update core voltages when data is available. */

static struct acpu_level acpu_freq_tbl[] = {

static struct acpu_level acpu_freq_tbl[] __initdata = {

	{ 0, { STBY_KHZ, QSB,   0, 0, 0x00 }, L2(0),   900000 },

	{ 1, {   384000, PLL_8, 0, 2, 0x00 }, L2(1),   900000 },

	{ 1, {   432000, HFPLL, 2, 0, 0x20 }, L2(5),   925000 },
@@ -126,14 +123,20 @@ static struct acpu_level acpu_freq_tbl[] = { 
	{ 0, { 0 } }

};



static struct acpuclk_krait_params acpuclk_8627_params = {

static struct pvs_table pvs_tables[NUM_PVS] __initdata = {

	[PVS_SLOW]    = { acpu_freq_tbl, sizeof(acpu_freq_tbl) },

	[PVS_NOMINAL] = { acpu_freq_tbl, sizeof(acpu_freq_tbl) },

	[PVS_FAST]    = { acpu_freq_tbl, sizeof(acpu_freq_tbl) },

};



static struct acpuclk_krait_params acpuclk_8627_params __initdata = {

	.scalable = scalable,

	.pvs_acpu_freq_tbl[PVS_SLOW] = acpu_freq_tbl,

	.pvs_acpu_freq_tbl[PVS_NOMINAL] = acpu_freq_tbl,

	.pvs_acpu_freq_tbl[PVS_FAST] = acpu_freq_tbl,

	.scalable_size = sizeof(scalable),

	.hfpll_data = &hfpll_data,

	.pvs_tables = pvs_tables,

	.l2_freq_tbl = l2_freq_tbl,

	.l2_freq_tbl_size = ARRAY_SIZE(l2_freq_tbl),

	.bus_scale_data = &bus_scale_data,

	.l2_freq_tbl_size = sizeof(l2_freq_tbl),

	.bus_scale = &bus_scale_data,

	.qfprom_phys_base = 0x00700000,

};

arch/arm/mach-msm/acpuclock-8930.c

+20 −17
Original line number Diff line number Diff line
@@ -27,7 +27,7 @@ 
#define LVL_NOM		RPM_VREG_CORNER_NOMINAL

#define LVL_HIGH	RPM_VREG_CORNER_HIGH



static struct hfpll_data hfpll_data = {

static struct hfpll_data hfpll_data __initdata = {

	.mode_offset = 0x00,

	.l_offset = 0x08,

	.m_offset = 0x0C,
@@ -43,10 +43,9 @@ static struct hfpll_data hfpll_data = { 
	.vdd[HFPLL_VDD_NOM]  = LVL_NOM,

};



static struct scalable scalable[] = {

static struct scalable scalable[] __initdata = {

	[CPU0] = {

		.hfpll_phys_base = 0x00903200,

		.hfpll_data = &hfpll_data,

		.aux_clk_sel_phys = 0x02088014,

		.aux_clk_sel = 3,

		.l2cpmr_iaddr = 0x4501,
@@ -57,7 +56,6 @@ static struct scalable scalable[] = { 
	},

	[CPU1] = {

		.hfpll_phys_base = 0x00903300,

		.hfpll_data = &hfpll_data,

		.aux_clk_sel_phys = 0x02098014,

		.aux_clk_sel = 3,

		.l2cpmr_iaddr = 0x5501,
@@ -68,7 +66,6 @@ static struct scalable scalable[] = { 
	},

	[L2] = {

		.hfpll_phys_base = 0x00903400,

		.hfpll_data = &hfpll_data,

		.aux_clk_sel_phys = 0x02011028,

		.aux_clk_sel = 3,

		.l2cpmr_iaddr = 0x0500,
@@ -76,7 +73,7 @@ static struct scalable scalable[] = { 
	},

};



static struct msm_bus_paths bw_level_tbl[] = {

static struct msm_bus_paths bw_level_tbl[] __initdata = {

	[0] =  BW_MBPS(640), /* At least  80 MHz on bus. */

	[1] = BW_MBPS(1064), /* At least 133 MHz on bus. */

	[2] = BW_MBPS(1600), /* At least 200 MHz on bus. */
@@ -87,7 +84,7 @@ static struct msm_bus_paths bw_level_tbl[] = { 
	[7] = BW_MBPS(4264), /* At least 533 MHz on bus. */

};



static struct msm_bus_scale_pdata bus_scale_data = {

static struct msm_bus_scale_pdata bus_scale_data __initdata = {

	.usecase = bw_level_tbl,

	.num_usecases = ARRAY_SIZE(bw_level_tbl),

	.active_only = 1,
@@ -95,7 +92,7 @@ static struct msm_bus_scale_pdata bus_scale_data = { 
};



/* TODO: Update vdd_dig, vdd_mem and bw when data is available. */

static struct l2_level l2_freq_tbl[] = {

static struct l2_level l2_freq_tbl[] __initdata = {

	[0]  = { {STBY_KHZ, QSB,   0, 0, 0x00 },  LVL_NOM, 1050000, 0 },

	[1]  = { {  384000, PLL_8, 0, 2, 0x00 },  LVL_NOM, 1050000, 1 },

	[2]  = { {  432000, HFPLL, 2, 0, 0x20 },  LVL_NOM, 1050000, 2 },
@@ -115,7 +112,7 @@ static struct l2_level l2_freq_tbl[] = { 
	[16] = { { 1188000, HFPLL, 1, 0, 0x2C }, LVL_HIGH, 1150000, 7 },

};



static struct acpu_level acpu_freq_tbl_slow[] = {

static struct acpu_level acpu_freq_tbl_slow[] __initdata = {

	{ 0, { STBY_KHZ, QSB,   0, 0, 0x00 }, L2(0),   950000 },

	{ 1, {   384000, PLL_8, 0, 2, 0x00 }, L2(1),   950000 },

	{ 1, {   432000, HFPLL, 2, 0, 0x20 }, L2(6),   975000 },
@@ -136,7 +133,7 @@ static struct acpu_level acpu_freq_tbl_slow[] = { 
	{ 0, { 0 } }

};



static struct acpu_level acpu_freq_tbl_nom[] = {

static struct acpu_level acpu_freq_tbl_nom[] __initdata = {

	{ 0, { STBY_KHZ, QSB,   0, 0, 0x00 }, L2(0),   925000 },

	{ 1, {   384000, PLL_8, 0, 2, 0x00 }, L2(1),   925000 },

	{ 1, {   432000, HFPLL, 2, 0, 0x20 }, L2(6),   950000 },
@@ -157,7 +154,7 @@ static struct acpu_level acpu_freq_tbl_nom[] = { 
	{ 0, { 0 } }

};



static struct acpu_level acpu_freq_tbl_fast[] = {

static struct acpu_level acpu_freq_tbl_fast[] __initdata = {

	{ 0, { STBY_KHZ, QSB,   0, 0, 0x00 }, L2(0),   900000 },

	{ 1, {   384000, PLL_8, 0, 2, 0x00 }, L2(1),   900000 },

	{ 1, {   432000, HFPLL, 2, 0, 0x20 }, L2(6),   900000 },
@@ -178,14 +175,20 @@ static struct acpu_level acpu_freq_tbl_fast[] = { 
	{ 0, { 0 } }

};



static struct acpuclk_krait_params acpuclk_8930_params = {

static struct pvs_table pvs_tables[NUM_PVS] __initdata = {

	[PVS_SLOW]    = { acpu_freq_tbl_slow, sizeof(acpu_freq_tbl_slow) },

	[PVS_NOMINAL] = { acpu_freq_tbl_nom,  sizeof(acpu_freq_tbl_nom)  },

	[PVS_FAST]    = { acpu_freq_tbl_fast, sizeof(acpu_freq_tbl_fast) },

};



static struct acpuclk_krait_params acpuclk_8930_params __initdata = {

	.scalable = scalable,

	.pvs_acpu_freq_tbl[PVS_SLOW] = acpu_freq_tbl_slow,

	.pvs_acpu_freq_tbl[PVS_NOMINAL] = acpu_freq_tbl_nom,

	.pvs_acpu_freq_tbl[PVS_FAST] = acpu_freq_tbl_fast,

	.scalable_size = sizeof(scalable),

	.hfpll_data = &hfpll_data,

	.pvs_tables = pvs_tables,

	.l2_freq_tbl = l2_freq_tbl,

	.l2_freq_tbl_size = ARRAY_SIZE(l2_freq_tbl),

	.bus_scale_data = &bus_scale_data,

	.l2_freq_tbl_size = sizeof(l2_freq_tbl),

	.bus_scale = &bus_scale_data,

	.qfprom_phys_base = 0x00700000,

};

arch/arm/mach-msm/acpuclock-8960.c

+20 −17
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ 
#include "acpuclock.h"

#include "acpuclock-krait.h"



static struct hfpll_data hfpll_data = {

static struct hfpll_data hfpll_data __initdata = {

	.mode_offset = 0x00,

	.l_offset = 0x08,

	.m_offset = 0x0C,
@@ -37,10 +37,9 @@ static struct hfpll_data hfpll_data = { 
	.vdd[HFPLL_VDD_NOM]  = 1050000,

};



static struct scalable scalable[] = {

static struct scalable scalable[] __initdata = {

	[CPU0] = {

		.hfpll_phys_base = 0x00903200,

		.hfpll_data = &hfpll_data,

		.aux_clk_sel_phys = 0x02088014,

		.aux_clk_sel = 3,

		.l2cpmr_iaddr = 0x4501,
@@ -52,7 +51,6 @@ static struct scalable scalable[] = { 
	},

	[CPU1] = {

		.hfpll_phys_base = 0x00903300,

		.hfpll_data = &hfpll_data,

		.aux_clk_sel_phys = 0x02098014,

		.aux_clk_sel = 3,

		.l2cpmr_iaddr = 0x5501,
@@ -64,7 +62,6 @@ static struct scalable scalable[] = { 
	},

	[L2] = {

		.hfpll_phys_base = 0x00903400,

		.hfpll_data = &hfpll_data,

		.aux_clk_sel_phys = 0x02011028,

		.aux_clk_sel = 3,

		.l2cpmr_iaddr = 0x0500,
@@ -73,7 +70,7 @@ static struct scalable scalable[] = { 
	},

};



static struct msm_bus_paths bw_level_tbl[] = {

static struct msm_bus_paths bw_level_tbl[] __initdata = {

	[0] =  BW_MBPS(640), /* At least  80 MHz on bus. */

	[1] = BW_MBPS(1064), /* At least 133 MHz on bus. */

	[2] = BW_MBPS(1600), /* At least 200 MHz on bus. */
@@ -83,14 +80,14 @@ static struct msm_bus_paths bw_level_tbl[] = { 
	[6] = BW_MBPS(3936), /* At least 492 MHz on bus. */

};



static struct msm_bus_scale_pdata bus_scale_data = {

static struct msm_bus_scale_pdata bus_scale_data __initdata = {

	.usecase = bw_level_tbl,

	.num_usecases = ARRAY_SIZE(bw_level_tbl),

	.active_only = 1,

	.name = "acpuclk-8960",

};



static struct l2_level l2_freq_tbl[] = {

static struct l2_level l2_freq_tbl[] __initdata = {

	[0]  = { {STBY_KHZ, QSB,   0, 0, 0x00 }, 1050000, 1050000, 0 },

	[1]  = { {  384000, PLL_8, 0, 2, 0x00 }, 1050000, 1050000, 1 },

	[2]  = { {  432000, HFPLL, 2, 0, 0x20 }, 1050000, 1050000, 2 },
@@ -113,7 +110,7 @@ static struct l2_level l2_freq_tbl[] = { 
	[19] = { { 1350000, HFPLL, 1, 0, 0x32 }, 1150000, 1150000, 6 },

};



static struct acpu_level acpu_freq_tbl_slow[] = {

static struct acpu_level acpu_freq_tbl_slow[] __initdata = {

	{ 0, { STBY_KHZ, QSB,   0, 0, 0x00 }, L2(0),   950000 },

	{ 1, {   384000, PLL_8, 0, 2, 0x00 }, L2(1),   950000 },

	{ 0, {   432000, HFPLL, 2, 0, 0x20 }, L2(7),   975000 },
@@ -140,7 +137,7 @@ static struct acpu_level acpu_freq_tbl_slow[] = { 
	{ 0, { 0 } }

};



static struct acpu_level acpu_freq_tbl_nom[] = {

static struct acpu_level acpu_freq_tbl_nom[] __initdata = {

	{ 0, { STBY_KHZ, QSB,   0, 0, 0x00 }, L2(0),   900000 },

	{ 1, {   384000, PLL_8, 0, 2, 0x00 }, L2(1),   900000 },

	{ 0, {   432000, HFPLL, 2, 0, 0x20 }, L2(7),   925000 },
@@ -167,7 +164,7 @@ static struct acpu_level acpu_freq_tbl_nom[] = { 
	{ 0, { 0 } }

};



static struct acpu_level acpu_freq_tbl_fast[] = {

static struct acpu_level acpu_freq_tbl_fast[] __initdata = {

	{ 0, { STBY_KHZ, QSB,   0, 0, 0x00 }, L2(0),   850000 },

	{ 1, {   384000, PLL_8, 0, 2, 0x00 }, L2(1),   850000 },

	{ 0, {   432000, HFPLL, 2, 0, 0x20 }, L2(7),   875000 },
@@ -194,14 +191,20 @@ static struct acpu_level acpu_freq_tbl_fast[] = { 
	{ 0, { 0 } }

};



static struct acpuclk_krait_params acpuclk_8960_params = {

static struct pvs_table pvs_tables[NUM_PVS] __initdata = {

	[PVS_SLOW]    = { acpu_freq_tbl_slow, sizeof(acpu_freq_tbl_slow) },

	[PVS_NOMINAL] = { acpu_freq_tbl_nom,  sizeof(acpu_freq_tbl_nom)  },

	[PVS_FAST]    = { acpu_freq_tbl_fast, sizeof(acpu_freq_tbl_fast) },

};



static struct acpuclk_krait_params acpuclk_8960_params __initdata = {

	.scalable = scalable,

	.pvs_acpu_freq_tbl[PVS_SLOW] = acpu_freq_tbl_slow,

	.pvs_acpu_freq_tbl[PVS_NOMINAL] = acpu_freq_tbl_nom,

	.pvs_acpu_freq_tbl[PVS_FAST] = acpu_freq_tbl_fast,

	.scalable_size = sizeof(scalable),

	.hfpll_data = &hfpll_data,

	.pvs_tables = pvs_tables,

	.l2_freq_tbl = l2_freq_tbl,

	.l2_freq_tbl_size = ARRAY_SIZE(l2_freq_tbl),

	.bus_scale_data = &bus_scale_data,

	.l2_freq_tbl_size = sizeof(l2_freq_tbl),

	.bus_scale = &bus_scale_data,

	.qfprom_phys_base = 0x00700000,

};

arch/arm/mach-msm/acpuclock-8974.c

+18 −17
Original line number Diff line number Diff line
@@ -28,7 +28,7 @@ 
#define LVL_NOM		RPM_REGULATOR_CORNER_NORMAL

#define LVL_HIGH	RPM_REGULATOR_CORNER_SUPER_TURBO



static struct hfpll_data hfpll_data = {

static struct hfpll_data hfpll_data __initdata = {

	.mode_offset = 0x00,

	.l_offset = 0x04,

	.m_offset = 0x08,
@@ -42,10 +42,9 @@ static struct hfpll_data hfpll_data = { 
	.vdd[HFPLL_VDD_NOM]  = LVL_NOM,

};



static struct scalable scalable[] = {

static struct scalable scalable[] __initdata = {

	[CPU0] = {

		.hfpll_phys_base = 0xF908A000,

		.hfpll_data = &hfpll_data,

		.l2cpmr_iaddr = 0x4501,

		.vreg[VREG_CORE] = { "krait0",     1050000, 3200000 },

		.vreg[VREG_MEM]  = { "krait0_mem", 1050000 },
@@ -55,7 +54,6 @@ static struct scalable scalable[] = { 
	},

	[CPU1] = {

		.hfpll_phys_base = 0xF909A000,

		.hfpll_data = &hfpll_data,

		.l2cpmr_iaddr = 0x5501,

		.vreg[VREG_CORE] = { "krait1",     1050000, 3200000 },

		.vreg[VREG_MEM]  = { "krait1_mem", 1050000 },
@@ -65,7 +63,6 @@ static struct scalable scalable[] = { 
	},

	[CPU2] = {

		.hfpll_phys_base = 0xF90AA000,

		.hfpll_data = &hfpll_data,

		.l2cpmr_iaddr = 0x6501,

		.vreg[VREG_CORE] = { "krait2",     1050000, 3200000 },

		.vreg[VREG_MEM]  = { "krait2_mem", 1050000 },
@@ -75,7 +72,6 @@ static struct scalable scalable[] = { 
	},

	[CPU3] = {

		.hfpll_phys_base = 0xF90BA000,

		.hfpll_data = &hfpll_data,

		.l2cpmr_iaddr = 0x7501,

		.vreg[VREG_CORE] = { "krait3",     1050000, 3200000 },

		.vreg[VREG_MEM]  = { "krait3_mem", 1050000 },
@@ -85,14 +81,13 @@ static struct scalable scalable[] = { 
	},

	[L2] = {

		.hfpll_phys_base = 0xF9016000,

		.hfpll_data = &hfpll_data,

		.l2cpmr_iaddr = 0x0500,

		.vreg[VREG_HFPLL_A] = { "l2_hfpll_a", 2150000 },

		.vreg[VREG_HFPLL_B] = { "l2_hfpll_b", 1800000 },

	},

};



static struct msm_bus_paths bw_level_tbl[] = {

static struct msm_bus_paths bw_level_tbl[] __initdata = {

	[0] =  BW_MBPS(400), /* At least  50 MHz on bus. */

	[1] =  BW_MBPS(800), /* At least 100 MHz on bus. */

	[2] = BW_MBPS(1334), /* At least 167 MHz on bus. */
@@ -100,14 +95,14 @@ static struct msm_bus_paths bw_level_tbl[] = { 
	[4] = BW_MBPS(3200), /* At least 333 MHz on bus. */

};



static struct msm_bus_scale_pdata bus_scale_data = {

static struct msm_bus_scale_pdata bus_scale_data __initdata = {

	.usecase = bw_level_tbl,

	.num_usecases = ARRAY_SIZE(bw_level_tbl),

	.active_only = 1,

	.name = "acpuclk-8974",

};



static struct l2_level l2_freq_tbl[] = {

static struct l2_level l2_freq_tbl[] __initdata = {

	[0]  = { {STBY_KHZ, QSB,   0, 0,   0 }, LVL_LOW, 1050000, 0 },

	[1]  = { {  300000, PLL_0, 0, 2,   0 }, LVL_LOW, 1050000, 2 },

	[2]  = { {  384000, HFPLL, 2, 0,  40 }, LVL_NOM, 1050000, 2 },
@@ -122,7 +117,7 @@ static struct l2_level l2_freq_tbl[] = { 
	[11] = { { 1036800, HFPLL, 1, 0,  54 }, LVL_NOM, 1050000, 4 },

};



static struct acpu_level acpu_freq_tbl[] = {

static struct acpu_level acpu_freq_tbl[] __initdata = {

	{ 0, {STBY_KHZ, QSB,   0, 0,   0 }, L2(0),  1050000 },

	{ 1, {  300000, PLL_0, 0, 2,   0 }, L2(1),  1050000 },

	{ 1, {  384000, HFPLL, 2, 0,  40 }, L2(2),  1050000 },
@@ -138,14 +133,20 @@ static struct acpu_level acpu_freq_tbl[] = { 
	{ 0, { 0 } }

};



static struct acpuclk_krait_params acpuclk_8974_params = {

static struct pvs_table pvs_tables[NUM_PVS]  __initdata = {

	[PVS_SLOW]    = { acpu_freq_tbl, sizeof(acpu_freq_tbl) },

	[PVS_NOMINAL] = { acpu_freq_tbl, sizeof(acpu_freq_tbl)  },

	[PVS_FAST]    = { acpu_freq_tbl, sizeof(acpu_freq_tbl) },

};



static struct acpuclk_krait_params acpuclk_8974_params __initdata = {

	.scalable = scalable,

	.pvs_acpu_freq_tbl[PVS_SLOW] = acpu_freq_tbl,

	.pvs_acpu_freq_tbl[PVS_NOMINAL] = acpu_freq_tbl,

	.pvs_acpu_freq_tbl[PVS_FAST] = acpu_freq_tbl,

	.scalable_size = sizeof(scalable),

	.hfpll_data = &hfpll_data,

	.pvs_tables = pvs_tables,

	.l2_freq_tbl = l2_freq_tbl,

	.l2_freq_tbl_size = ARRAY_SIZE(l2_freq_tbl),

	.bus_scale_data = &bus_scale_data,

	.l2_freq_tbl_size = sizeof(l2_freq_tbl),

	.bus_scale = &bus_scale_data,

	.qfprom_phys_base = 0xFC4A8000,

};