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Commit 8733edab authored by Taniya Das's avatar Taniya Das Committed by Gerrit - the friendly Code Review server
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clk: qcom: clock-8916: Add support for APSS cpu debug mux 



The GLB_CLK_DIAG register selects the test clock to be
output from the APCS to the chip's clock controller.
APSS debug mux will allow to measure the current cpu
and l2 frequency.

Change-Id: Ifa48719124e7abbdda2aaa36af60216502de75a8
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent d8b4f0b2

Documentation/devicetree/bindings/arm/msm/clock-controller.txt

+3 −2
Original line number Diff line number Diff line
@@ -10,13 +10,14 @@ the compatible string to indicate the revision. 


Required properties:

- compatible:		Must be one of "qcom,gcc-<target>",

			"qcom,mmsscc-<target>", "qcom,debugcc-<target>" or

			"qcom,mmsscc-<target>", "qcom,cc-debug-<target>" or

			"qcom,lpasscc-<target>" or qcom,gcc-mdss-<target>.

			<target> is the name of the Qualcomm SoC.

- reg:			Pairs of physical base addresses and region sizes of

			memory mapped registers.

- reg-names:		Names of the bases for the above registers. Currently,

			there is one expected base: "cc_base"

			there is one expected base: "cc_base". Optional

			reg-names are "apcs_base" and "meas".



Optional properties:

- vdd_dig-supply:	The digital logic rail supply.

arch/arm/boot/dts/qcom/msm8916.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -268,6 +268,7 @@ 
	clock_debug: qcom,cc-debug@1874000 {

		compatible = "qcom,cc-debug-8916";

		reg = <0x1874000 0x4>;

		reg-names = "cc_base";

		clocks = <&clock_rpm clk_rpm_debug_mux>;

		clock-names = "rpm_debug_mux";

		#clock-cells = <1>;

drivers/clk/qcom/clock-gcc-8916.c

+113 −0
Original line number Diff line number Diff line
@@ -2322,6 +2322,99 @@ static struct branch_clk gcc_venus0_vcodec0_clk = { 
static struct mux_clk gcc_debug_mux;

static struct clk_ops clk_ops_debug_mux;



static void __iomem *meas_base;



static struct measure_clk apc0_m_clk = {

	.c = {

		.ops = &clk_ops_empty,

		.dbg_name = "apc0_m_clk",

		CLK_INIT(apc0_m_clk.c),

	},

};



static struct measure_clk apc1_m_clk = {

	.c = {

		.ops = &clk_ops_empty,

		.dbg_name = "apc1_m_clk",

		CLK_INIT(apc1_m_clk.c),

	},

};



static struct measure_clk apc2_m_clk = {

	.c = {

		.ops = &clk_ops_empty,

		.dbg_name = "apc2_m_clk",

		CLK_INIT(apc2_m_clk.c),

	},

};



static struct measure_clk apc3_m_clk = {

	.c = {

		.ops = &clk_ops_empty,

		.dbg_name = "apc3_m_clk",

		CLK_INIT(apc3_m_clk.c),

	},

};



static struct measure_clk l2_m_clk = {

	.c = {

		.ops = &clk_ops_empty,

		.dbg_name = "l2_m_clk",

		CLK_INIT(l2_m_clk.c),

	},

};



static struct mux_clk apss_debug_ter_mux = {

	.ops = &mux_reg_ops,

	.mask = 0x3,

	.shift = 8,

	MUX_SRC_LIST(

		{&apc0_m_clk.c, 0},

		{&apc1_m_clk.c, 1},

		{&apc2_m_clk.c, 2},

		{&apc3_m_clk.c, 3},

	),

	.base = &meas_base,

	.c = {

		.dbg_name = "apss_debug_ter_mux",

		.ops = &clk_ops_gen_mux,

		CLK_INIT(apss_debug_ter_mux.c),

	},

};



static struct mux_clk apss_debug_sec_mux = {

	.ops = &mux_reg_ops,

	.mask = 0x7,

	.shift = 12,

	MUX_SRC_LIST(

		{&apss_debug_ter_mux.c, 0},

		{&l2_m_clk.c, 1},

	),

	.rec_set_par = 1,

	.base = &meas_base,

	.c = {

		.dbg_name = "apss_debug_sec_mux",

		.ops = &clk_ops_gen_mux,

		CLK_INIT(apss_debug_sec_mux.c),

	},

};



static struct mux_clk apss_debug_pri_mux = {

	.ops = &mux_reg_ops,

	.mask = 0x3,

	.shift = 16,

	MUX_SRC_LIST(

		{&apss_debug_sec_mux.c, 0},

	),

	.rec_set_par = 1,

	.base = &meas_base,

	.c = {

		.dbg_name = "apss_debug_pri_mux",

		.ops = &clk_ops_gen_mux,

		CLK_INIT(apss_debug_pri_mux.c),

	},

};



static struct measure_clk_data debug_mux_priv = {

	.cxo = &xo_clk_src.c,

	.plltest_reg = GCC_PLLTEST_PAD_CFG,
@@ -2360,6 +2453,7 @@ static struct mux_clk gcc_debug_mux = { 
	.base = &virt_bases[GCC_BASE],

	MUX_SRC_LIST(

		{&rpm_debug_clk.c,			0xFFFF},

		{&apss_debug_pri_mux.c,			0x016A},

		{&gcc_gp1_clk.c,			0x0010},

		{&gcc_gp2_clk.c,			0x0011},

		{&gcc_gp3_clk.c,			0x0012},
@@ -2731,11 +2825,30 @@ arch_initcall(msm_gcc_init); 


static struct clk_lookup msm_clocks_measure[] = {

	CLK_LOOKUP_OF("measure", gcc_debug_mux, "debug"),

	CLK_LIST(apss_debug_pri_mux),

	CLK_LIST(apc0_m_clk),

	CLK_LIST(apc1_m_clk),

	CLK_LIST(apc2_m_clk),

	CLK_LIST(apc3_m_clk),

	CLK_LIST(l2_m_clk),

};



static int msm_clock_debug_probe(struct platform_device *pdev)

{

	int ret;

	struct resource *res;



	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "meas");

	if (!res) {

		dev_err(&pdev->dev, "GLB clock diag base not defined.\n");

		return -EINVAL;

	}



	meas_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));

	if (!meas_base) {

		dev_err(&pdev->dev, "Unable to map GLB clock diag base.\n");

		return -ENOMEM;

	}



	clk_ops_debug_mux = clk_ops_gen_mux;

	clk_ops_debug_mux.get_rate = measure_get_rate;

include/dt-bindings/clock/msm-clocks-8916.h

+9 −0
Original line number Diff line number Diff line
@@ -206,5 +206,14 @@ 
#define clk_gcc_debug_mux			0x8121ac15

#define clk_rpm_debug_mux			0x25cd1f3a

#define clk_wcnss_m_clk				0x709f430b

#define clk_apss_debug_pri_mux			0xc691ff55

#define clk_apss_debug_sec_mux			0xc0b680f9

#define clk_apss_debug_ter_mux			0x32041c48

#define clk_apc0_m_clk				0xce1e9473

#define clk_apc1_m_clk				0x990fbaf7

#define clk_apc2_m_clk				0x252cd4ae

#define clk_apc3_m_clk				0x78c64486

#define clk_l2_m_clk				0x4bedf4d0





#endif