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Commit 8696a7c2 authored by Venkat Gopalakrishnan's avatar Venkat Gopalakrishnan
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mmc: sdhci-msm: Cancel disabling AHB bus transfer 



The SDCC5 controller and later revisions can handle reset in middle of
an ongoing transfer without the need to disable AHB bus transaction
separately. Disable the workaround for the newer revisions of the core.

Change-Id: I825bff8cccfc3084af9bbbf67a241bb73647872f
Signed-off-by: default avatarVenkat Gopalakrishnan <venkatg@codeaurora.org>
parent d6e87cbf

drivers/mmc/host/sdhci-msm.c

+13 −4
Original line number Diff line number Diff line
@@ -149,7 +149,11 @@ enum sdc_mpm_pin_state { 
#define CORE_TESTBUS_SEL2	(1 << CORE_TESTBUS_SEL2_BIT)



#define CORE_MCI_VERSION		0x050

#define CORE_VERSION_310	0x10000011

#define CORE_VERSION_STEP_MASK		0x0000FFFF

#define CORE_VERSION_MINOR_MASK		0x0FFF0000

#define CORE_VERSION_MINOR_SHIFT	16

#define CORE_VERSION_MAJOR_MASK		0xF0000000

#define CORE_VERSION_MAJOR_SHIFT	28



/*

 * Waiting until end of potential AHB access for data:
@@ -2694,10 +2698,15 @@ static void sdhci_msm_disable_data_xfer(struct sdhci_host *host) 
	u32 value;

	int ret;

	u32 version;

	u8 major;



	version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION);

	/* Core version 3.1.0 doesn't need this workaround */

	if (version == CORE_VERSION_310)

	major = (version & CORE_VERSION_MAJOR_MASK) >>

			CORE_VERSION_MAJOR_SHIFT;



	/* Starting with SDCC 5 controller (core major version = 1)

	 * and later revisions don't require this workaround */

	if (major >= 1)

		return;



	value = readl_relaxed(msm_host->core_mem + CORE_MCI_DATA_CTRL);