Loading drivers/iommu/msm_iommu-v1.c +19 −3 Original line number Diff line number Diff line Loading @@ -396,7 +396,6 @@ static int __flush_iotlb(struct iommu_domain *domain) SET_TLBIASID(iommu_drvdata->cb_base, ctx_drvdata->num, ctx_drvdata->asid); mb(); __sync_tlb(iommu_drvdata, ctx_drvdata->num); __disable_clocks(iommu_drvdata); } Loading @@ -410,7 +409,8 @@ fail: */ static void __reset_iommu(struct msm_iommu_drvdata *iommu_drvdata) { int i, smt_size; int i, smt_size, res; unsigned long val; void __iomem *base = iommu_drvdata->base; /* SMMU_ACR is an implementation defined register. Loading @@ -421,7 +421,15 @@ static void __reset_iommu(struct msm_iommu_drvdata *iommu_drvdata) SET_CR2(base, 0); SET_GFAR(base, 0); SET_GFSRRESTORE(base, 0); /* Invalidate the entire non-secure TLB */ SET_TLBIALLNSNH(base, 0); SET_TLBGSYNC(base, 0); res = readl_tight_poll_timeout(GLB_REG(TLBGSTATUS, base), val, (val & TLBGSTATUS_GSACTIVE) == 0, 5000000); if (res) BUG(); smt_size = GET_IDR0_NUMSMRG(base); for (i = 0; i < smt_size; i++) Loading Loading @@ -523,7 +531,6 @@ static void __reset_context(struct msm_iommu_drvdata *iommu_drvdata, int ctx) SET_PAR(base, ctx, 0); SET_PRRR(base, ctx, 0); SET_SCTLR(base, ctx, 0); SET_TLBIALL(base, ctx, 0); SET_TTBCR(base, ctx, 0); SET_TTBR0(base, ctx, 0); SET_TTBR1(base, ctx, 0); Loading Loading @@ -720,6 +727,14 @@ static void __program_context(struct msm_iommu_drvdata *iommu_drvdata, msm_iommu_assign_ASID(iommu_drvdata, ctx_drvdata, priv); /* Ensure that ASID assignment has completed before we use * ASID for TLB invalidation. Here, mb() is required because * both these registers are separated by more than 1KB. */ mb(); SET_TLBIASID(iommu_drvdata->cb_base, ctx_drvdata->num, ctx_drvdata->asid); __sync_tlb(iommu_drvdata, ctx_drvdata->num); /* Enable the MMU */ SET_CB_SCTLR_M(cb_base, ctx, 1); mb(); Loading Loading @@ -901,6 +916,7 @@ static void msm_iommu_detach_dev(struct iommu_domain *domain, SET_TLBIASID(iommu_drvdata->cb_base, ctx_drvdata->num, ctx_drvdata->asid); __sync_tlb(iommu_drvdata, ctx_drvdata->num); ctx_drvdata->asid = -1; Loading drivers/iommu/msm_iommu_hw-v1.h +2 −2 Original line number Diff line number Diff line Loading @@ -106,7 +106,7 @@ do { \ #define SET_TLBIALLNSNH(b, v) SET_GLOBAL_REG(TLBIALLNSNH, (b), (v)) #define SET_TLBIALLH(b, v) SET_GLOBAL_REG(TLBIALLH, (b), (v)) #define SET_TLBGSYNC(b, v) SET_GLOBAL_REG(TLBGSYNC, (b), (v)) #define SET_TLBGSTATUS(b, v) SET_GLOBAL_REG(TLBSTATUS, (b), (v)) #define SET_TLBGSTATUS(b, v) SET_GLOBAL_REG(TLBGSTATUS, (b), (v)) #define SET_TLBIVAH(b, v) SET_GLOBAL_REG(TLBIVAH, (b), (v)) #define SET_GATS1UR(b, v) SET_GLOBAL_REG(GATS1UR, (b), (v)) #define SET_GATS1UW(b, v) SET_GLOBAL_REG(GATS1UW, (b), (v)) Loading Loading @@ -145,7 +145,7 @@ do { \ #define GET_TLBIALLNSNH(b) GET_GLOBAL_REG(TLBIALLNSNH, (b)) #define GET_TLBIALLH(b) GET_GLOBAL_REG(TLBIALLH, (b)) #define GET_TLBGSYNC(b) GET_GLOBAL_REG(TLBGSYNC, (b)) #define GET_TLBGSTATUS(b) GET_GLOBAL_REG(TLBSTATUS, (b)) #define GET_TLBGSTATUS(b) GET_GLOBAL_REG(TLBGSTATUS, (b)) #define GET_TLBIVAH(b) GET_GLOBAL_REG(TLBIVAH, (b)) #define GET_GATS1UR(b) GET_GLOBAL_REG(GATS1UR, (b)) #define GET_GATS1UW(b) GET_GLOBAL_REG(GATS1UW, (b)) Loading Loading
drivers/iommu/msm_iommu-v1.c +19 −3 Original line number Diff line number Diff line Loading @@ -396,7 +396,6 @@ static int __flush_iotlb(struct iommu_domain *domain) SET_TLBIASID(iommu_drvdata->cb_base, ctx_drvdata->num, ctx_drvdata->asid); mb(); __sync_tlb(iommu_drvdata, ctx_drvdata->num); __disable_clocks(iommu_drvdata); } Loading @@ -410,7 +409,8 @@ fail: */ static void __reset_iommu(struct msm_iommu_drvdata *iommu_drvdata) { int i, smt_size; int i, smt_size, res; unsigned long val; void __iomem *base = iommu_drvdata->base; /* SMMU_ACR is an implementation defined register. Loading @@ -421,7 +421,15 @@ static void __reset_iommu(struct msm_iommu_drvdata *iommu_drvdata) SET_CR2(base, 0); SET_GFAR(base, 0); SET_GFSRRESTORE(base, 0); /* Invalidate the entire non-secure TLB */ SET_TLBIALLNSNH(base, 0); SET_TLBGSYNC(base, 0); res = readl_tight_poll_timeout(GLB_REG(TLBGSTATUS, base), val, (val & TLBGSTATUS_GSACTIVE) == 0, 5000000); if (res) BUG(); smt_size = GET_IDR0_NUMSMRG(base); for (i = 0; i < smt_size; i++) Loading Loading @@ -523,7 +531,6 @@ static void __reset_context(struct msm_iommu_drvdata *iommu_drvdata, int ctx) SET_PAR(base, ctx, 0); SET_PRRR(base, ctx, 0); SET_SCTLR(base, ctx, 0); SET_TLBIALL(base, ctx, 0); SET_TTBCR(base, ctx, 0); SET_TTBR0(base, ctx, 0); SET_TTBR1(base, ctx, 0); Loading Loading @@ -720,6 +727,14 @@ static void __program_context(struct msm_iommu_drvdata *iommu_drvdata, msm_iommu_assign_ASID(iommu_drvdata, ctx_drvdata, priv); /* Ensure that ASID assignment has completed before we use * ASID for TLB invalidation. Here, mb() is required because * both these registers are separated by more than 1KB. */ mb(); SET_TLBIASID(iommu_drvdata->cb_base, ctx_drvdata->num, ctx_drvdata->asid); __sync_tlb(iommu_drvdata, ctx_drvdata->num); /* Enable the MMU */ SET_CB_SCTLR_M(cb_base, ctx, 1); mb(); Loading Loading @@ -901,6 +916,7 @@ static void msm_iommu_detach_dev(struct iommu_domain *domain, SET_TLBIASID(iommu_drvdata->cb_base, ctx_drvdata->num, ctx_drvdata->asid); __sync_tlb(iommu_drvdata, ctx_drvdata->num); ctx_drvdata->asid = -1; Loading
drivers/iommu/msm_iommu_hw-v1.h +2 −2 Original line number Diff line number Diff line Loading @@ -106,7 +106,7 @@ do { \ #define SET_TLBIALLNSNH(b, v) SET_GLOBAL_REG(TLBIALLNSNH, (b), (v)) #define SET_TLBIALLH(b, v) SET_GLOBAL_REG(TLBIALLH, (b), (v)) #define SET_TLBGSYNC(b, v) SET_GLOBAL_REG(TLBGSYNC, (b), (v)) #define SET_TLBGSTATUS(b, v) SET_GLOBAL_REG(TLBSTATUS, (b), (v)) #define SET_TLBGSTATUS(b, v) SET_GLOBAL_REG(TLBGSTATUS, (b), (v)) #define SET_TLBIVAH(b, v) SET_GLOBAL_REG(TLBIVAH, (b), (v)) #define SET_GATS1UR(b, v) SET_GLOBAL_REG(GATS1UR, (b), (v)) #define SET_GATS1UW(b, v) SET_GLOBAL_REG(GATS1UW, (b), (v)) Loading Loading @@ -145,7 +145,7 @@ do { \ #define GET_TLBIALLNSNH(b) GET_GLOBAL_REG(TLBIALLNSNH, (b)) #define GET_TLBIALLH(b) GET_GLOBAL_REG(TLBIALLH, (b)) #define GET_TLBGSYNC(b) GET_GLOBAL_REG(TLBGSYNC, (b)) #define GET_TLBGSTATUS(b) GET_GLOBAL_REG(TLBSTATUS, (b)) #define GET_TLBGSTATUS(b) GET_GLOBAL_REG(TLBGSTATUS, (b)) #define GET_TLBIVAH(b) GET_GLOBAL_REG(TLBIVAH, (b)) #define GET_GATS1UR(b) GET_GLOBAL_REG(GATS1UR, (b)) #define GET_GATS1UW(b) GET_GLOBAL_REG(GATS1UW, (b)) Loading