clock-alpha-pll: Add FSM voting mode support

Some PLLs are controlled through FSM voting registers instead of
performing power up/down sequence directly in software.

Add enable/disable support for PLLs under FSM voting mode.

Change-Id: I46f1328af2f15461f983930ef4f217741802b514
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>