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Commit 840a8311 authored by Carter Cooper's avatar Carter Cooper Committed by Stephen Boyd
Browse files

msm: kgsl: Count user and kernel performance counters seperately 



Rather than just storing if the performance counter was referenced by the
kernel in a flag, keep track of user space and kernel space references
seperately.  This allows finer grained manipulations on the performance
counters (ie when allowed to be released).  This is needed to be able to
turn off certain performance counters when fault tolerance is disabled
at runtime.

Change-Id: I7b5593459e64557dabd594aeb6532a0c9af6a9c5
Signed-off-by: default avatarCarter Cooper <ccooper@codeaurora.org>
parent 52896064

drivers/gpu/msm/adreno.c

+35 −22
Original line number Diff line number Diff line
@@ -445,8 +445,11 @@ int adreno_perfcounter_get(struct adreno_device *adreno_dev, 
	for (i = 0; i < group->reg_count; i++) {

		if (group->regs[i].countable == countable) {

			/* Countable already associated with counter */

			group->regs[i].refcount++;

			group->regs[i].flags |= flags;

			if (flags & PERFCOUNTER_FLAG_KERNEL)

				group->regs[i].kernelcount++;

			else

				group->regs[i].usercount++;



			if (offset)

				*offset = group->regs[i].offset;

			return 0;
@@ -463,14 +466,20 @@ int adreno_perfcounter_get(struct adreno_device *adreno_dev, 


	/* initialize the new counter */

	group->regs[empty].countable = countable;

	group->regs[empty].refcount = 1;



	/* set initial kernel and user count */

	if (flags & PERFCOUNTER_FLAG_KERNEL) {

		group->regs[empty].kernelcount = 1;

		group->regs[empty].usercount = 0;

	} else {

		group->regs[empty].kernelcount = 0;

		group->regs[empty].usercount = 1;

	}



	/* enable the new counter */

	adreno_dev->gpudev->perfcounter_enable(adreno_dev, groupid, empty,

		countable);



	group->regs[empty].flags = flags;



	if (offset)

		*offset = group->regs[empty].offset;
@@ -483,12 +492,13 @@ int adreno_perfcounter_get(struct adreno_device *adreno_dev, 
 * @adreno_dev: Adreno device to configure

 * @groupid: Desired performance counter group

 * @countable: Countable desired to be freed from a  counter

 * @flags: Flag to determine if kernel or user space request

 *

 * Put a performance counter/countable pair that was previously received.  If

 * noone else is using the countable, free up the counter for others.

 */

int adreno_perfcounter_put(struct adreno_device *adreno_dev,

	unsigned int groupid, unsigned int countable)

	unsigned int groupid, unsigned int countable, unsigned int flags)

{

	struct adreno_perfcounters *counters = adreno_dev->gpudev->perfcounters;

	struct adreno_perfcount_group *group;
@@ -504,24 +514,27 @@ int adreno_perfcounter_put(struct adreno_device *adreno_dev, 


	group = &(counters->groups[groupid]);



	for (i = 0; i < group->reg_count; i++) {

		if (group->regs[i].countable == countable) {

			if (group->regs[i].refcount > 0) {

				group->regs[i].refcount--;



	/*

				 * book keeping to ensure we never free a

				 * perf counter used by kernel

	 * Find if the counter/countable pair is used currently.

	 * Start cycling through registers in the bank.

	 */

				if (group->regs[i].flags &&

					group->regs[i].refcount == 0)

					group->regs[i].refcount++;

	for (i = 0; i < group->reg_count; i++) {

		/* check if countable assigned is what we are looking for */

		if (group->regs[i].countable == countable) {

			/* found pair, book keep count based on request type */

			if (flags & PERFCOUNTER_FLAG_KERNEL &&

					group->regs[i].kernelcount > 0)

				group->regs[i].kernelcount--;

			else if (group->regs[i].usercount > 0)

				group->regs[i].usercount--;

			else

				break;



				/* make available if not used */

				if (group->regs[i].refcount == 0)

			/* mark available if not used anymore */

			if (group->regs[i].kernelcount == 0 &&

					group->regs[i].usercount == 0)

				group->regs[i].countable =

					KGSL_PERFCOUNTER_NOT_USED;

			}



			return 0;

		}
@@ -4082,7 +4095,7 @@ static long adreno_ioctl(struct kgsl_device_private *dev_priv, 
	case IOCTL_KGSL_PERFCOUNTER_PUT: {

		struct kgsl_perfcounter_put *put = data;

		result = adreno_perfcounter_put(adreno_dev, put->groupid,

			put->countable);

			put->countable, PERFCOUNTER_FLAG_NONE);

		break;

	}

	case IOCTL_KGSL_PERFCOUNTER_QUERY: {

drivers/gpu/msm/adreno.h

+5 −4
Original line number Diff line number Diff line
@@ -141,14 +141,15 @@ struct adreno_device { 
/**

 * struct adreno_perfcount_register: register state

 * @countable: countable the register holds

 * @refcount: number of users of the register

 * @kernelcount: number of user space users of the register

 * @usercount: number of kernel users of the register

 * @offset: register hardware offset

 */

struct adreno_perfcount_register {

	unsigned int countable;

	unsigned int refcount;

	unsigned int kernelcount;

	unsigned int usercount;

	unsigned int offset;

	unsigned int flags;

};



/**
@@ -418,7 +419,7 @@ int adreno_perfcounter_get(struct adreno_device *adreno_dev, 
	unsigned int flags);



int adreno_perfcounter_put(struct adreno_device *adreno_dev,

	unsigned int groupid, unsigned int countable);

	unsigned int groupid, unsigned int countable, unsigned int flags);



int adreno_soft_reset(struct kgsl_device *device);

drivers/gpu/msm/adreno_a3xx.c

+50 −50
Original line number Diff line number Diff line
@@ -3152,97 +3152,97 @@ static struct { 
 */



static struct adreno_perfcount_register a3xx_perfcounters_cp[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_CP_0_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_CP_0_LO },

};



static struct adreno_perfcount_register a3xx_perfcounters_rbbm[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_RBBM_0_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_RBBM_1_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RBBM_0_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RBBM_1_LO },

};



static struct adreno_perfcount_register a3xx_perfcounters_pc[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_PC_0_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_PC_1_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_PC_2_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_PC_3_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PC_0_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PC_1_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PC_2_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PC_3_LO },

};



static struct adreno_perfcount_register a3xx_perfcounters_vfd[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_VFD_0_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_VFD_1_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_VFD_0_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_VFD_1_LO },

};



static struct adreno_perfcount_register a3xx_perfcounters_hlsq[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_HLSQ_0_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_HLSQ_1_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_HLSQ_2_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_HLSQ_3_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_HLSQ_4_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_HLSQ_5_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_0_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_1_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_2_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_3_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_4_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_5_LO },

};



static struct adreno_perfcount_register a3xx_perfcounters_vpc[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_VPC_0_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_VPC_1_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_VPC_0_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_VPC_1_LO },

};



static struct adreno_perfcount_register a3xx_perfcounters_tse[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_TSE_0_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_TSE_1_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TSE_0_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TSE_1_LO },

};



static struct adreno_perfcount_register a3xx_perfcounters_ras[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_RAS_0_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_RAS_1_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RAS_0_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RAS_1_LO },

};



static struct adreno_perfcount_register a3xx_perfcounters_uche[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_UCHE_0_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_UCHE_1_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_UCHE_2_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_UCHE_3_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_UCHE_4_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_UCHE_5_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_0_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_1_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_2_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_3_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_4_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_5_LO },

};



static struct adreno_perfcount_register a3xx_perfcounters_tp[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_TP_0_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_TP_1_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_TP_2_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_TP_3_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_TP_4_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_TP_5_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_0_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_1_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_2_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_3_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_4_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_5_LO },

};



static struct adreno_perfcount_register a3xx_perfcounters_sp[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_SP_0_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_SP_1_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_SP_2_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_SP_3_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_SP_4_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_SP_5_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_SP_6_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_SP_7_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_0_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_1_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_2_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_3_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_4_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_5_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_6_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_7_LO },

};



static struct adreno_perfcount_register a3xx_perfcounters_rb[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_RB_0_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_RB_1_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RB_0_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RB_1_LO },

};



static struct adreno_perfcount_register a3xx_perfcounters_pwr[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_PWR_0_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_RBBM_PERFCTR_PWR_1_LO, 0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PWR_0_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PWR_1_LO },

};



static struct adreno_perfcount_register a3xx_perfcounters_vbif[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_VBIF_PERF_CNT0_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_VBIF_PERF_CNT1_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF_PERF_CNT0_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF_PERF_CNT1_LO },

};

static struct adreno_perfcount_register a3xx_perfcounters_vbif_pwr[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_VBIF_PERF_PWR_CNT0_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_VBIF_PERF_PWR_CNT1_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, A3XX_VBIF_PERF_PWR_CNT2_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF_PERF_PWR_CNT0_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF_PERF_PWR_CNT1_LO },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF_PERF_PWR_CNT2_LO },

};



static struct adreno_perfcount_group a3xx_perfcounter_groups[] = {