Merge "crypto: msm: Add aead hmac-sha256 support" (839d317c) · Commits · e / devices / android_kernel_sony_msm8994

drivers/crypto/msm/qce.h

+2 −1

Original line number	Diff line number	Diff line
		@@ -149,6 +149,7 @@ struct qce_req {
		enum qce_cipher_alg_enum alg; /* cipher algorithms*/
		enum qce_cipher_dir_enum dir; /* encryption? decryption? */
		enum qce_cipher_mode_enum mode; /* algorithm mode */
		enum qce_hash_alg_enum auth_alg;/* authentication algorithm for aead */
		unsigned char authkey; / authentication key */
		unsigned int authklen; /* authentication key kength */
		unsigned int authsize; /* authentication key kength */

drivers/crypto/msm/qce50.c

+138 −124

Original line number	Diff line number	Diff line
		@@ -411,13 +411,15 @@ static struct qce_cmdlist_info *_ce_get_aead_cmdlistinfo(
		switch (creq->alg) {
		case CIPHER_ALG_DES:
		switch (creq->mode) {
		case QCE_MODE_ECB:
		return &pce_dev->ce_sps.
		cmdlistptr.aead_hmac_sha1_ecb_des;
		break;
		case QCE_MODE_CBC:
		if (creq->auth_alg == QCE_HASH_SHA1_HMAC)
		return &pce_dev->ce_sps.
		cmdlistptr.aead_hmac_sha1_cbc_des;
		else if (creq->auth_alg == QCE_HASH_SHA256_HMAC)
		return &pce_dev->ce_sps.
		cmdlistptr.aead_hmac_sha256_cbc_des;
		else
		return NULL;
		break;
		default:
		return NULL;
		@@ -425,13 +427,15 @@ static struct qce_cmdlist_info *_ce_get_aead_cmdlistinfo(
		break;
		case CIPHER_ALG_3DES:
		switch (creq->mode) {
		case QCE_MODE_ECB:
		return &pce_dev->ce_sps.
		cmdlistptr.aead_hmac_sha1_ecb_3des;
		break;
		case QCE_MODE_CBC:
		if (creq->auth_alg == QCE_HASH_SHA1_HMAC)
		return &pce_dev->ce_sps.
		cmdlistptr.aead_hmac_sha1_cbc_3des;
		else if (creq->auth_alg == QCE_HASH_SHA256_HMAC)
		return &pce_dev->ce_sps.
		cmdlistptr.aead_hmac_sha256_cbc_3des;
		else
		return NULL;
		break;
		default:
		return NULL;
		@@ -439,25 +443,29 @@ static struct qce_cmdlist_info *_ce_get_aead_cmdlistinfo(
		break;
		case CIPHER_ALG_AES:
		switch (creq->mode) {
		case QCE_MODE_ECB:
		if (creq->encklen == AES128_KEY_SIZE)
		return &pce_dev->ce_sps.
		cmdlistptr.aead_hmac_sha1_ecb_aes_128;
		else if (creq->encklen == AES256_KEY_SIZE)
		return &pce_dev->ce_sps.
		cmdlistptr.aead_hmac_sha1_ecb_aes_256;
		case QCE_MODE_CBC:
		if (creq->encklen == AES128_KEY_SIZE) {
		if (creq->auth_alg == QCE_HASH_SHA1_HMAC)
		return &pce_dev->ce_sps.cmdlistptr.
		aead_hmac_sha1_cbc_aes_128;
		else if (creq->auth_alg ==
		QCE_HASH_SHA256_HMAC)
		return &pce_dev->ce_sps.cmdlistptr.
		aead_hmac_sha256_cbc_aes_128;
		else
		return NULL;
		break;
		case QCE_MODE_CBC:
		if (creq->encklen == AES128_KEY_SIZE)
		return &pce_dev->ce_sps.
		cmdlistptr.aead_hmac_sha1_cbc_aes_128;
		else if (creq->encklen == AES256_KEY_SIZE)
		return &pce_dev->ce_sps.
		cmdlistptr.aead_hmac_sha1_cbc_aes_256;
		} else if (creq->encklen == AES256_KEY_SIZE) {
		if (creq->auth_alg == QCE_HASH_SHA1_HMAC)
		return &pce_dev->ce_sps.cmdlistptr.
		aead_hmac_sha1_cbc_aes_256;
		else if (creq->auth_alg ==
		QCE_HASH_SHA256_HMAC)
		return &pce_dev->ce_sps.cmdlistptr.
		aead_hmac_sha256_cbc_aes_256;
		else
		return NULL;
		} else
		return NULL;
		break;
		default:
		return NULL;
		@@ -508,15 +516,12 @@ static int _ce_setup_aead(struct qce_device pce_dev, struct qce_req q_req,
		}

		switch (q_req->mode) {
		case QCE_MODE_ECB:
		case QCE_MODE_CBC:
		case QCE_MODE_CTR:
		pce_dev->mode = q_req->mode;
		break;
		default:
		return -EINVAL;
		}

		if (q_req->mode != QCE_MODE_ECB) {
		_byte_stream_to_net_words(enciv32, q_req->iv, ivsize);
		pce = cmdlistinfo->encr_cntr_iv;
		@@ -542,15 +547,20 @@ static int _ce_setup_aead(struct qce_device pce_dev, struct qce_req q_req,
		encr_cfg &= ~(1 << CRYPTO_ENCODE);
		pce->data = encr_cfg;

		/* we only support sha1-hmac at this point */
		/* we only support sha1-hmac and sha256-hmac at this point */
		_byte_stream_to_net_words(mackey32, q_req->authkey,
		q_req->authklen);
		pce = cmdlistinfo->auth_key;
		for (i = 0; i < authk_size_in_word; i++, pce++)
		pce->data = mackey32[i];
		pce = cmdlistinfo->auth_iv;

		if (q_req->auth_alg == QCE_HASH_SHA1_HMAC)
		for (i = 0; i < 5; i++, pce++)
		pce->data = _std_init_vector_sha1[i];
		else
		for (i = 0; i < 8; i++, pce++)
		pce->data = _std_init_vector_sha256[i];

		/* write auth_bytecnt 0/1, start with 0 */
		pce = cmdlistinfo->auth_bytecount;
		@@ -1337,9 +1347,6 @@ static int _ce_setup_aead_direct(struct qce_device *pce_dev,
		case CIPHER_ALG_DES:

		switch (q_req->mode) {
		case QCE_MODE_ECB:
		encr_cfg = pce_dev->reg.encr_cfg_des_ecb;
		break;
		case QCE_MODE_CBC:
		encr_cfg = pce_dev->reg.encr_cfg_des_cbc;
		break;
		@@ -1353,9 +1360,6 @@ static int _ce_setup_aead_direct(struct qce_device *pce_dev,
		case CIPHER_ALG_3DES:

		switch (q_req->mode) {
		case QCE_MODE_ECB:
		encr_cfg = pce_dev->reg.encr_cfg_3des_ecb;
		break;
		case QCE_MODE_CBC:
		encr_cfg = pce_dev->reg.encr_cfg_3des_cbc;
		break;
		@@ -1370,14 +1374,6 @@ static int _ce_setup_aead_direct(struct qce_device *pce_dev,
		case CIPHER_ALG_AES:

		switch (q_req->mode) {
		case QCE_MODE_ECB:
		if (key_size == AES128_KEY_SIZE)
		encr_cfg = pce_dev->reg.encr_cfg_aes_ecb_128;
		else if (key_size == AES256_KEY_SIZE)
		encr_cfg = pce_dev->reg.encr_cfg_aes_ecb_256;
		else
		return -EINVAL;
		break;
		case QCE_MODE_CBC:
		if (key_size == AES128_KEY_SIZE)
		encr_cfg = pce_dev->reg.encr_cfg_aes_cbc_128;
		@@ -1423,16 +1419,24 @@ static int _ce_setup_aead_direct(struct qce_device *pce_dev,
		encr_cfg \|= (1 << CRYPTO_ENCODE);
		QCE_WRITE_REG(encr_cfg, pce_dev->iobase + CRYPTO_ENCR_SEG_CFG_REG);

		/* we only support sha1-hmac at this point */
		/* we only support sha1-hmac and sha256-hmc at this point */
		_byte_stream_to_net_words(mackey32, q_req->authkey,
		q_req->authklen);
		for (i = 0; i < authk_size_in_word; i++)
		QCE_WRITE_REG(mackey32[i], pce_dev->iobase +
		(CRYPTO_AUTH_KEY0_REG + i * sizeof(uint32_t)));

		if (q_req->auth_alg == QCE_HASH_SHA1_HMAC) {
		for (i = 0; i < 5; i++)
		QCE_WRITE_REG(_std_init_vector_sha1[i], pce_dev->iobase +
		QCE_WRITE_REG(_std_init_vector_sha1[i],
		pce_dev->iobase +
		(CRYPTO_AUTH_IV0_REG + i * sizeof(uint32_t)));
		} else {
		for (i = 0; i < 8; i++)
		QCE_WRITE_REG(_std_init_vector_sha256[i],
		pce_dev->iobase +
		(CRYPTO_AUTH_IV0_REG + i * sizeof(uint32_t)));
		}

		/* write auth_bytecnt 0/1, start with 0 */
		QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_AUTH_BYTECNT0_REG);
		@@ -1446,10 +1450,10 @@ static int _ce_setup_aead_direct(struct qce_device *pce_dev,
		QCE_WRITE_REG(coffset & 0xffff, pce_dev->iobase +
		CRYPTO_ENCR_SEG_START_REG);

		a_cfg = (CRYPTO_AUTH_MODE_HMAC << CRYPTO_AUTH_MODE) \|
		(CRYPTO_AUTH_SIZE_SHA1 << CRYPTO_AUTH_SIZE) \|
		(1 << CRYPTO_LAST) \| (1 << CRYPTO_FIRST) \|
		(CRYPTO_AUTH_ALG_SHA << CRYPTO_AUTH_ALG);
		if (q_req->auth_alg == QCE_HASH_SHA1_HMAC)
		a_cfg = pce_dev->reg.auth_cfg_aead_sha1_hmac;
		else
		a_cfg = pce_dev->reg.auth_cfg_aead_sha256_hmac;

		if (q_req->dir == QCE_ENCRYPT)
		a_cfg \|= (CRYPTO_AUTH_POS_AFTER << CRYPTO_AUTH_POS);
		@@ -3401,7 +3405,8 @@ static int _setup_aead_cmdlistptrs(struct qce_device *pdev,
		unsigned char **pvaddr,
		uint32_t alg,
		uint32_t mode,
		uint32_t key_size)
		uint32_t key_size,
		bool sha1)
		{
		struct sps_command_element *ce_vaddr;
		uint32_t ce_vaddr_start;
		@@ -3425,18 +3430,18 @@ static int _setup_aead_cmdlistptrs(struct qce_device *pdev,

		switch (mode) {

		case QCE_MODE_ECB:
		cmdlistptr->aead_hmac_sha1_ecb_des.cmdlist =
		(uint32_t)ce_vaddr;
		pcl_info = &(cmdlistptr->aead_hmac_sha1_ecb_des);
		encr_cfg = pdev->reg.encr_cfg_des_ecb;

		break;

		case QCE_MODE_CBC:
		if (sha1) {
		cmdlistptr->aead_hmac_sha1_cbc_des.cmdlist =
		(uint32_t)ce_vaddr;
		pcl_info = &(cmdlistptr->aead_hmac_sha1_cbc_des);
		pcl_info = &(cmdlistptr->
		aead_hmac_sha1_cbc_des);
		} else {
		cmdlistptr->aead_hmac_sha256_cbc_des.cmdlist =
		(uint32_t)ce_vaddr;
		pcl_info = &(cmdlistptr->
		aead_hmac_sha256_cbc_des);
		}
		encr_cfg = pdev->reg.encr_cfg_des_cbc;
		break;
		default:
		@@ -3450,18 +3455,18 @@ static int _setup_aead_cmdlistptrs(struct qce_device *pdev,
		case CIPHER_ALG_3DES:
		switch (mode) {

		case QCE_MODE_ECB:
		cmdlistptr->aead_hmac_sha1_ecb_3des.cmdlist =
		(uint32_t)ce_vaddr;
		pcl_info = &(cmdlistptr->aead_hmac_sha1_ecb_3des);
		encr_cfg = pdev->reg.encr_cfg_3des_ecb;

		break;

		case QCE_MODE_CBC:
		if (sha1) {
		cmdlistptr->aead_hmac_sha1_cbc_3des.cmdlist =
		(uint32_t)ce_vaddr;
		pcl_info = &(cmdlistptr->aead_hmac_sha1_cbc_3des);
		pcl_info = &(cmdlistptr->
		aead_hmac_sha1_cbc_3des);
		} else {
		cmdlistptr->aead_hmac_sha256_cbc_3des.cmdlist =
		(uint32_t)ce_vaddr;
		pcl_info = &(cmdlistptr->
		aead_hmac_sha256_cbc_3des);
		}
		encr_cfg = pdev->reg.encr_cfg_3des_cbc;
		break;
		default:
		@@ -3475,38 +3480,36 @@ static int _setup_aead_cmdlistptrs(struct qce_device *pdev,
		case CIPHER_ALG_AES:
		switch (mode) {

		case QCE_MODE_ECB:
		if (key_size == AES128_KEY_SIZE) {
		cmdlistptr->aead_hmac_sha1_ecb_aes_128.cmdlist =
		(uint32_t)ce_vaddr;
		pcl_info = &(cmdlistptr->
		aead_hmac_sha1_ecb_aes_128);

		encr_cfg = pdev->reg.encr_cfg_aes_ecb_128;

		} else if (key_size == AES256_KEY_SIZE) {
		cmdlistptr->aead_hmac_sha1_ecb_aes_256.cmdlist =
		(uint32_t)ce_vaddr;
		pcl_info = &(cmdlistptr->
		aead_hmac_sha1_ecb_aes_256);
		encr_cfg = pdev->reg.encr_cfg_aes_ecb_256;
		} else {
		return -EINVAL;
		}
		break;

		case QCE_MODE_CBC:
		if (key_size == AES128_KEY_SIZE) {
		cmdlistptr->aead_hmac_sha1_cbc_aes_128.cmdlist =
		(uint32_t)ce_vaddr;
		if (sha1) {
		cmdlistptr->
		aead_hmac_sha1_cbc_aes_128.
		cmdlist = (uint32_t)ce_vaddr;
		pcl_info = &(cmdlistptr->
		aead_hmac_sha1_cbc_aes_128);
		} else {
		cmdlistptr->
		aead_hmac_sha256_cbc_aes_128.
		cmdlist = (uint32_t)ce_vaddr;
		pcl_info = &(cmdlistptr->
		aead_hmac_sha256_cbc_aes_128);
		}
		encr_cfg = pdev->reg.encr_cfg_aes_cbc_128;
		} else if (key_size == AES256_KEY_SIZE) {
		cmdlistptr->aead_hmac_sha1_cbc_aes_256.cmdlist =
		(uint32_t)ce_vaddr;
		if (sha1) {
		cmdlistptr->
		aead_hmac_sha1_cbc_aes_256.
		cmdlist = (uint32_t)ce_vaddr;
		pcl_info = &(cmdlistptr->
		aead_hmac_sha1_cbc_aes_256);
		} else {
		cmdlistptr->
		aead_hmac_sha256_cbc_aes_256.
		cmdlist = (uint32_t)ce_vaddr;
		pcl_info = &(cmdlistptr->
		aead_hmac_sha256_cbc_aes_256);
		}
		encr_cfg = pdev->reg.encr_cfg_aes_cbc_256;
		} else {
		return -EINVAL;
		@@ -3548,7 +3551,10 @@ static int _setup_aead_cmdlistptrs(struct qce_device *pdev,
		0, NULL);
		};

		if (sha1)
		iv_reg = 5;
		else
		iv_reg = 8;
		qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_IV0_REG, 0,
		&pcl_info->auth_iv);
		for (i = 1; i < iv_reg; i++)
		@@ -3577,12 +3583,20 @@ static int _setup_aead_cmdlistptrs(struct qce_device *pdev,
		qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_SEG_START_REG, 0,
		&pcl_info->encr_seg_start);

		if (sha1)
		qce_add_cmd_element(
		pdev,
		&ce_vaddr,
		CRYPTO_AUTH_SEG_CFG_REG,
		pdev->reg.auth_cfg_aead_sha1_hmac,
		&pcl_info->auth_seg_cfg);
		else
		qce_add_cmd_element(
		pdev,
		&ce_vaddr,
		CRYPTO_AUTH_SEG_CFG_REG,
		pdev->reg.auth_cfg_aead_sha256_hmac,
		&pcl_info->auth_seg_cfg);

		qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_SEG_SIZE_REG, 0,
		&pcl_info->auth_seg_size);
		@@ -3957,21 +3971,21 @@ static int qce_setup_cmdlistptrs(struct qce_device *pdev,
		_setup_auth_cmdlistptrs(pdev, pvaddr, QCE_HASH_AES_CMAC, false);

		_setup_aead_cmdlistptrs(pdev, pvaddr, CIPHER_ALG_DES, QCE_MODE_CBC,
		DES_KEY_SIZE);
		_setup_aead_cmdlistptrs(pdev, pvaddr, CIPHER_ALG_DES, QCE_MODE_ECB,
		DES_KEY_SIZE);
		DES_KEY_SIZE, true);
		_setup_aead_cmdlistptrs(pdev, pvaddr, CIPHER_ALG_3DES, QCE_MODE_CBC,
		DES3_EDE_KEY_SIZE, true);
		_setup_aead_cmdlistptrs(pdev, pvaddr, CIPHER_ALG_AES, QCE_MODE_CBC,
		AES128_KEY_SIZE, true);
		_setup_aead_cmdlistptrs(pdev, pvaddr, CIPHER_ALG_AES, QCE_MODE_CBC,
		AES256_KEY_SIZE, true);
		_setup_aead_cmdlistptrs(pdev, pvaddr, CIPHER_ALG_DES, QCE_MODE_CBC,
		DES_KEY_SIZE, false);
		_setup_aead_cmdlistptrs(pdev, pvaddr, CIPHER_ALG_3DES, QCE_MODE_CBC,
		DES3_EDE_KEY_SIZE);
		_setup_aead_cmdlistptrs(pdev, pvaddr, CIPHER_ALG_3DES, QCE_MODE_ECB,
		DES3_EDE_KEY_SIZE);
		DES3_EDE_KEY_SIZE, false);
		_setup_aead_cmdlistptrs(pdev, pvaddr, CIPHER_ALG_AES, QCE_MODE_CBC,
		AES128_KEY_SIZE);
		_setup_aead_cmdlistptrs(pdev, pvaddr, CIPHER_ALG_AES, QCE_MODE_ECB,
		AES128_KEY_SIZE);
		AES128_KEY_SIZE, false);
		_setup_aead_cmdlistptrs(pdev, pvaddr, CIPHER_ALG_AES, QCE_MODE_CBC,
		AES256_KEY_SIZE);
		_setup_aead_cmdlistptrs(pdev, pvaddr, CIPHER_ALG_AES, QCE_MODE_ECB,
		AES256_KEY_SIZE);
		AES256_KEY_SIZE, false);

		_setup_aead_ccm_cmdlistptrs(pdev, pvaddr, true);
		_setup_aead_ccm_cmdlistptrs(pdev, pvaddr, false);

drivers/crypto/msm/qce50.h

+4 −4

Original line number	Diff line number	Diff line
		@@ -107,10 +107,10 @@ struct qce_cmdlistptr_ops {
		struct qce_cmdlist_info aead_hmac_sha1_cbc_aes_256;
		struct qce_cmdlist_info aead_hmac_sha1_cbc_des;
		struct qce_cmdlist_info aead_hmac_sha1_cbc_3des;
		struct qce_cmdlist_info aead_hmac_sha1_ecb_aes_128;
		struct qce_cmdlist_info aead_hmac_sha1_ecb_aes_256;
		struct qce_cmdlist_info aead_hmac_sha1_ecb_des;
		struct qce_cmdlist_info aead_hmac_sha1_ecb_3des;
		struct qce_cmdlist_info aead_hmac_sha256_cbc_aes_128;
		struct qce_cmdlist_info aead_hmac_sha256_cbc_aes_256;
		struct qce_cmdlist_info aead_hmac_sha256_cbc_des;
		struct qce_cmdlist_info aead_hmac_sha256_cbc_3des;
		struct qce_cmdlist_info aead_aes_128_ccm;
		struct qce_cmdlist_info aead_aes_256_ccm;
		struct qce_cmdlist_info f8_kasumi;