Loading arch/arm/boot/dts/qcom/msm8994.dtsi +16 −0 Original line number Diff line number Diff line Loading @@ -208,6 +208,22 @@ ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; arm64-cpu-erp@f9100000 { compatible = "arm,arm64-cpu-erp"; reg = <0xf9100000 0x1000>; reg-names = "cci"; interrupts = <0 328 0>, <0 329 0>, <0 330 0>, <0 331 0>, <0 22 0>; interrupt-names = "pri-dbe-irq", "sec-dbe-irq", "pri-ext-irq", "sec-ext-irq", "cci-irq"; }; acc0:clock-controller@f908b004 { compatible = "qcom,arm-cortex-acc"; reg = <0xf9070000 0x1000>, Loading Loading
arch/arm/boot/dts/qcom/msm8994.dtsi +16 −0 Original line number Diff line number Diff line Loading @@ -208,6 +208,22 @@ ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; arm64-cpu-erp@f9100000 { compatible = "arm,arm64-cpu-erp"; reg = <0xf9100000 0x1000>; reg-names = "cci"; interrupts = <0 328 0>, <0 329 0>, <0 330 0>, <0 331 0>, <0 22 0>; interrupt-names = "pri-dbe-irq", "sec-dbe-irq", "pri-ext-irq", "sec-ext-irq", "cci-irq"; }; acc0:clock-controller@f908b004 { compatible = "qcom,arm-cortex-acc"; reg = <0xf9070000 0x1000>, Loading