Loading Documentation/devicetree/bindings/arm/msm/msm_iommu_domains.txt +16 −16 Original line number Diff line number Diff line Loading @@ -8,43 +8,43 @@ instead of individual devices/contexts. Required properties - compatible: "qcom,iommu-domains" - compatible: "qti,iommu-domains" - At least one child that defines a domain is required with the following properties: - label: Name of the domain - qcom,iommu-contexts: List of phandles to context that belongs to - qti,iommu-contexts: List of phandles to context that belongs to this domain. Optional properties - qcom,virtual-addr-pool: List of <start_address size> pairs - qti,virtual-addr-pool: List of <start_address size> pairs that define the virtual address space for this domain. - qcom,secure-domain: boolean indicating that this is a secure - qti,secure-domain: boolean indicating that this is a secure domain that is to be programmed by Trustzone. - qcom,l2-redirect: boolean indicating that page tables should - qti,l2-redirect: boolean indicating that page tables should be cached in L2 cache. Example: qcom,iommu-domains { compatible = "qcom,iommu-domains"; qti,iommu-domains { compatible = "qti,iommu-domains"; qcom,iommu-domain1 { qti,iommu-domain1 { label = "lpass_secure"; qcom,iommu-contexts = <&lpass_q6_fw>; qcom,virtual-addr-pool = <0x00000000 0x0FFFFFFF qti,iommu-contexts = <&lpass_q6_fw>; qti,virtual-addr-pool = <0x00000000 0x0FFFFFFF 0xF0000000 0x0FFFFFFF>; }; qcom,iommu-domain2 { qti,iommu-domain2 { label = "lpass_audio"; qcom,iommu-contexts = <&lpass_audio_shared>; qcom,virtual-addr-pool = <0x10000000 0x0FFFFFFF>; qti,iommu-contexts = <&lpass_audio_shared>; qti,virtual-addr-pool = <0x10000000 0x0FFFFFFF>; }; qcom,iommu-domain3 { qti,iommu-domain3 { label = "lpass_video"; qcom,iommu-contexts = <&lpass_video_shared>; qcom,virtual-addr-pool = <0x20000000 0x0FFFFFFF>; qti,iommu-contexts = <&lpass_video_shared>; qti,virtual-addr-pool = <0x20000000 0x0FFFFFFF>; }; }; Documentation/devicetree/bindings/arm/msm/msm_tspp2.txt +8 −8 Original line number Diff line number Diff line Loading @@ -33,17 +33,17 @@ for more information on the following four properties: - qcom,msm-bus,num-paths - qcom,msm-bus,vectors-KBps: represents the bandwidths required for the above usecases. - qcom,iommu-hlos-group: Name of the Broadcast HLOS IOMMU domain as defined in - qti,iommu-hlos-group: Name of the Broadcast HLOS IOMMU domain as defined in <target>-iommu-domains.dtsi, (e.g. mpq8092-iommu-domains.dtsi). The Broadcast HLOS IOMMU domain includes a context bank and virtual address pools definitions, used for mapping non-secured pipe memory buffers. - qcom,iommu-hlos-partition: Partition number in the HLOS IOMMU domain. - qcom,iommu-cpz-group: Name of the Broadcast CPZ IOMMU domain as defined in - qti,iommu-hlos-partition: Partition number in the HLOS IOMMU domain. - qti,iommu-cpz-group: Name of the Broadcast CPZ IOMMU domain as defined in <target>-iommu-domains.dtsi, (e.g. mpq8092-iommu-domains.dtsi). The Broadcast CPZ IOMMU domain includes a context bank and virtual address pool definitions, used for mapping secured pipe memory buffers. - qcom,iommu-cpz-partition: Partition number in the CPZ IOMMU domain. - qti,iommu-cpz-partition: Partition number in the CPZ IOMMU domain. Example (for MPQ8092 platform, avaialble at mpq8092.dtsi): Loading Loading @@ -79,10 +79,10 @@ Example (for MPQ8092 platform, avaialble at mpq8092.dtsi): <96 512 0 0>, /* No vote */ <96 512 1024 1024>, /* Register access only. 8Mbps should be more than enough */ <96 512 24576 61440>; /* Max. bandwidth required is 480Mbps */ qcom,iommu-hlos-group = "bcast_hlos"; qcom,iommu-hlos-partition = <0>; qcom,iommu-cpz-group = "bcast_cpz"; qcom,iommu-cpz-partition = <0>; qti,iommu-hlos-group = "bcast_hlos"; qti,iommu-hlos-partition = <0>; qti,iommu-cpz-group = "bcast_cpz"; qti,iommu-cpz-partition = <0>; }; Documentation/devicetree/bindings/iommu/msm_iommu_v0.txt +18 −18 Original line number Diff line number Diff line Loading @@ -2,27 +2,27 @@ Required properties: - compatible : one of: - "qcom,msm-smmu-v0" - "qti,msm-smmu-v0" - reg : offset and length of the register set for the device. - qcom,glb-offset : Offset for the global register base. - qti,glb-offset : Offset for the global register base. Optional properties: - interrupts : should contain the performance monitor overflow interrupt number. - qcom,iommu-pmu-ngroups: Number of Performance Monitor Unit (PMU) groups. - qcom,iommu-pmu-ncounters: Number of PMU counters per group. - qcom,iommu-pmu-event-classes: List of event classes supported. - qcom,needs-alt-core-clk : boolean to enable the secondary core clock for - qti,iommu-pmu-ngroups: Number of Performance Monitor Unit (PMU) groups. - qti,iommu-pmu-ncounters: Number of PMU counters per group. - qti,iommu-pmu-event-classes: List of event classes supported. - qti,needs-alt-core-clk : boolean to enable the secondary core clock for access to the IOMMU configuration registers - Bus scaling properties: See msm_bus.txt - qcom,msm-enable-remote-spinlock : boolean to enable use of remote spinlock - qti,msm-enable-remote-spinlock : boolean to enable use of remote spinlock - List of sub nodes, one for each of the translation context banks supported. Required properties for each sub-node: - compatible : "qcom,msm-smmu-v0-ctx" - compatible : "qti,msm-smmu-v0-ctx" - reg : offset and length of the register set for the context bank. - interrupts : should contain the context bank interrupt. - qcom,iommu-ctx-mids : List of machine identifiers associated with this - qti,iommu-ctx-mids : List of machine identifiers associated with this translation context. - label : Name of the context bank Loading @@ -31,23 +31,23 @@ Optional properties: Example: qcom,iommu@fd000000 { compatible = "qcom,msm-smmu-v0"; qti,iommu@fd000000 { compatible = "qti,msm-smmu-v0"; #address-cells = <1>; #size-cells = <1>; ranges; reg = <0xfd890000 0x10000>; qcom,glb-offset = <0xF000>; qti,glb-offset = <0xF000>; interrupts = <0 38 0>; qcom,iommu-pmu-ngroups = <1>; qcom,iommu-pmu-ncounters = <4>; qcom,iommu-pmu-event-classes = <0x08 qti,iommu-pmu-ngroups = <1>; qti,iommu-pmu-ncounters = <4>; qti,iommu-pmu-event-classes = <0x08 0x11>; qcom,iommu-ctx@fd000000 { compatible = "qcom,msm-smmu-v0-ctx"; qti,iommu-ctx@fd000000 { compatible = "qti,msm-smmu-v0-ctx"; reg = <0xfd000000 0x1000>; interrupts = <0 250 0>; qcom,iommu-ctx-mids = <0 3>; qti,iommu-ctx-mids = <0 3>; label = "a_label"; }; Documentation/devicetree/bindings/iommu/msm_iommu_v1.txt +33 −33 Original line number Diff line number Diff line Loading @@ -2,7 +2,7 @@ Required properties: - compatible : one of: - "qcom,msm-smmu-v1" - "qti,msm-smmu-v1" - reg : offset and length of the register set for the device. Optional offset and length for clock register for additional clock that needs to be turned on for access to this IOMMU. Loading @@ -10,11 +10,11 @@ Required properties: - label: name of this IOMMU instance. Optional properties: - qcom,iommu-secure-id : Secure identifier for the IOMMU block - qcom,secure-context : boolean indicating that a context is secure and - qti,iommu-secure-id : Secure identifier for the IOMMU block - qti,secure-context : boolean indicating that a context is secure and programmed by the secure environment. - qcom,vdd-supply: Regulator needed to access IOMMU - qcom,alt-vdd-supply : Alternative regulator needed to access IOMMU - qti,vdd-supply: Regulator needed to access IOMMU - qti,alt-vdd-supply : Alternative regulator needed to access IOMMU configuration registers. - interrupts : Interrupt numbers for permormance and global fault interrupts - interrupt-names: Refers to the interrupts number mentioned above. Loading @@ -23,77 +23,77 @@ Optional properties: "global_client_NS_irq" : the global client non-secure interrupt number "global_cfg_S_irq" : the global config secure interrupt number "global_client_S_irq" : the global client secure interrupt number - qcom,iommu-enable-halt : Enable halt of the IOMMU before programming certain 19 - qti,iommu-enable-halt : Enable halt of the IOMMU before programming certain 19 registers - qcom,iommu-pmu-ngroups: Number of Performance Monitor Unit (PMU) groups. - qcom,iommu-pmu-ncounters: Number of PMU counters per group. - qcom,iommu-pmu-event-classes: List of event classes supported. - qti,iommu-pmu-ngroups: Number of Performance Monitor Unit (PMU) groups. - qti,iommu-pmu-ncounters: Number of PMU counters per group. - qti,iommu-pmu-event-classes: List of event classes supported. - Bus scaling properties: See msm_bus.txt - List of sub nodes, one for each of the translation context banks supported. Each sub node has the following required properties: - compatible : "qcom,msm-smmu-v1-ctx" - compatible : "qti,msm-smmu-v1-ctx" - reg : offset and length of the register set for the context bank. - interrupts : should contain the context bank interrupt. If this is a secure context bank, this should be a list of 2 3-tuples where the first is the non-secure interrupt, and the second is the secure interrupt. - qcom,iommu-ctx-sids : List of stream identifiers associated with this - qti,iommu-ctx-sids : List of stream identifiers associated with this translation context. - label : Name of the context bank - vdd-supply : vdd-supply: phandle to GDSC regulator controlling this IOMMU. Optional properties: - qcom,needs-alt-core-clk : boolean to enable the secondary core clock for - qti,needs-alt-core-clk : boolean to enable the secondary core clock for access to the IOMMU configuration registers - qcom,needs-alt-iface-clk : boolean to enable the secondary iface clock for - qti,needs-alt-iface-clk : boolean to enable the secondary iface clock for access to the IOMMU configuration registers - qcom,iommu-bfb-regs : An array of unsigned 32-bit integers corresponding to - qti,iommu-bfb-regs : An array of unsigned 32-bit integers corresponding to BFB register addresses that need to be configured for performance tuning purposes. If this property is present, the qcom,iommu-bfb-data must also be purposes. If this property is present, the qti,iommu-bfb-data must also be present. Register addresses are specified as an offset from the base of the IOMMU hardware block. This property may be omitted if no BFB register configuration needs to be done for a particular IOMMU hardware instance. The registers specified by this property shall fall within the IOMMU implementation-defined register region. - qcom,iommu-bfb-data : An array of unsigned 32-bit integers representing the - qti,iommu-bfb-data : An array of unsigned 32-bit integers representing the values to be programmed into the corresponding registers given by the qcom,iommu-bfb-regs property. If this property is present, the qcom,iommu-bfb-regs property shall also be present, and the lengths of both qti,iommu-bfb-regs property. If this property is present, the qti,iommu-bfb-regs property shall also be present, and the lengths of both properties shall be the same. - qcom,iommu-lpae-bfb-regs : See description for qcom,iommu-bfb-regs. This is - qti,iommu-lpae-bfb-regs : See description for qti,iommu-bfb-regs. This is the same property except this is for IOMMU with LPAE support. - qcom,iommu-lpae-bfb-data : See description for qcom,iommu-bfb-data. This is - qti,iommu-lpae-bfb-data : See description for qti,iommu-bfb-data. This is the same property except this is for IOMMU with LPAE support. Example: qcom,iommu@fda64000 { compatible = "qcom,msm-smmu-v1"; qti,iommu@fda64000 { compatible = "qti,msm-smmu-v1"; reg = <0xfda64000 0x10000>; reg-names = "iommu_base"; vdd-supply = <&gdsc_iommu>; qcom,iommu-bfb-regs = <0x204c 0x2050>; qcom,iommu-bfb-data = <0xffff 0xffce>; qti,iommu-bfb-regs = <0x204c 0x2050>; qti,iommu-bfb-data = <0xffff 0xffce>; label = "iommu_0"; qcom,iommu-pmu-ngroups = <1>; qcom,iommu-pmu-ncounters = <8>; qcom,iommu-pmu-event-classes = <0x00, qti,iommu-pmu-ngroups = <1>; qti,iommu-pmu-ncounters = <8>; qti,iommu-pmu-event-classes = <0x00, 0x01>; qcom,iommu-ctx@fda6c000 { compatible = "qcom,msm-smmu-v1-ctx"; qti,iommu-ctx@fda6c000 { compatible = "qti,msm-smmu-v1-ctx"; reg = <0xfda6c000 0x1000>; interrupts = <0 70 0>; qcom,iommu-ctx-sids = <0 2>; qti,iommu-ctx-sids = <0 2>; label = "ctx_0"; }; qcom,iommu-ctx@fda6d000 { compatible = "qcom,msm-smmu-v1-ctx"; qti,iommu-ctx@fda6d000 { compatible = "qti,msm-smmu-v1-ctx"; reg = <0xfda6d000 0x1000>; interrupts = <0 71 0>; qcom,iommu-ctx-sids = <1>; qti,iommu-ctx-sids = <1>; label = "ctx_1"; }; }; arch/arm/boot/dts/qti/apq8084-iommu-domains.dtsi +23 −23 Original line number Diff line number Diff line Loading @@ -11,49 +11,49 @@ */ &soc { qcom,iommu-domains { compatible = "qcom,iommu-domains"; qti,iommu-domains { compatible = "qti,iommu-domains"; qcom,iommu-domain1 { qti,iommu-domain1 { label = "lpass_secure"; qcom,iommu-contexts = <&lpass_q6_fw>; qcom,virtual-addr-pool = <0x00000000 0x0FFFFFFF qti,iommu-contexts = <&lpass_q6_fw>; qti,virtual-addr-pool = <0x00000000 0x0FFFFFFF 0xF0000000 0x0FFFFFFF>; }; qcom,iommu-domain2 { qti,iommu-domain2 { label = "lpass_audio"; qcom,iommu-contexts = <&lpass_audio_shared qti,iommu-contexts = <&lpass_audio_shared &lpass_core_audio>; qcom,virtual-addr-pool = <0x10000000 0x0FFFFFFF>; qti,virtual-addr-pool = <0x10000000 0x0FFFFFFF>; }; venus_domain_ns: qcom,iommu-domain3 { venus_domain_ns: qti,iommu-domain3 { label = "venus_ns"; qcom,iommu-contexts = <&venus_ns>; qcom,virtual-addr-pool = <0x5dc00000 0x7f000000 qti,iommu-contexts = <&venus_ns>; qti,virtual-addr-pool = <0x5dc00000 0x7f000000 0xdcc00000 0x1000000>; }; venus_domain_sec_bitstream: qcom,iommu-domain4 { venus_domain_sec_bitstream: qti,iommu-domain4 { label = "venus_sec_bitstream"; qcom,iommu-contexts = <&venus_sec_bitstream>; qcom,virtual-addr-pool = <0x4b000000 0x12c00000>; qcom,secure-domain; qti,iommu-contexts = <&venus_sec_bitstream>; qti,virtual-addr-pool = <0x4b000000 0x12c00000>; qti,secure-domain; }; venus_domain_sec_pixel: qcom,iommu-domain5 { venus_domain_sec_pixel: qti,iommu-domain5 { label = "venus_sec_pixel"; qcom,iommu-contexts = <&venus_sec_pixel>; qcom,virtual-addr-pool = <0x25800000 0x25800000>; qcom,secure-domain; qti,iommu-contexts = <&venus_sec_pixel>; qti,virtual-addr-pool = <0x25800000 0x25800000>; qti,secure-domain; }; venus_domain_sec_non_pixel: qcom,iommu-domain6 { venus_domain_sec_non_pixel: qti,iommu-domain6 { label = "venus_sec_non_pixel"; qcom,iommu-contexts = <&venus_sec_non_pixel>; qcom,virtual-addr-pool = <0x1000000 0x24800000>; qcom,secure-domain; qti,iommu-contexts = <&venus_sec_non_pixel>; qti,virtual-addr-pool = <0x1000000 0x24800000>; qti,secure-domain; }; }; }; Loading
Documentation/devicetree/bindings/arm/msm/msm_iommu_domains.txt +16 −16 Original line number Diff line number Diff line Loading @@ -8,43 +8,43 @@ instead of individual devices/contexts. Required properties - compatible: "qcom,iommu-domains" - compatible: "qti,iommu-domains" - At least one child that defines a domain is required with the following properties: - label: Name of the domain - qcom,iommu-contexts: List of phandles to context that belongs to - qti,iommu-contexts: List of phandles to context that belongs to this domain. Optional properties - qcom,virtual-addr-pool: List of <start_address size> pairs - qti,virtual-addr-pool: List of <start_address size> pairs that define the virtual address space for this domain. - qcom,secure-domain: boolean indicating that this is a secure - qti,secure-domain: boolean indicating that this is a secure domain that is to be programmed by Trustzone. - qcom,l2-redirect: boolean indicating that page tables should - qti,l2-redirect: boolean indicating that page tables should be cached in L2 cache. Example: qcom,iommu-domains { compatible = "qcom,iommu-domains"; qti,iommu-domains { compatible = "qti,iommu-domains"; qcom,iommu-domain1 { qti,iommu-domain1 { label = "lpass_secure"; qcom,iommu-contexts = <&lpass_q6_fw>; qcom,virtual-addr-pool = <0x00000000 0x0FFFFFFF qti,iommu-contexts = <&lpass_q6_fw>; qti,virtual-addr-pool = <0x00000000 0x0FFFFFFF 0xF0000000 0x0FFFFFFF>; }; qcom,iommu-domain2 { qti,iommu-domain2 { label = "lpass_audio"; qcom,iommu-contexts = <&lpass_audio_shared>; qcom,virtual-addr-pool = <0x10000000 0x0FFFFFFF>; qti,iommu-contexts = <&lpass_audio_shared>; qti,virtual-addr-pool = <0x10000000 0x0FFFFFFF>; }; qcom,iommu-domain3 { qti,iommu-domain3 { label = "lpass_video"; qcom,iommu-contexts = <&lpass_video_shared>; qcom,virtual-addr-pool = <0x20000000 0x0FFFFFFF>; qti,iommu-contexts = <&lpass_video_shared>; qti,virtual-addr-pool = <0x20000000 0x0FFFFFFF>; }; };
Documentation/devicetree/bindings/arm/msm/msm_tspp2.txt +8 −8 Original line number Diff line number Diff line Loading @@ -33,17 +33,17 @@ for more information on the following four properties: - qcom,msm-bus,num-paths - qcom,msm-bus,vectors-KBps: represents the bandwidths required for the above usecases. - qcom,iommu-hlos-group: Name of the Broadcast HLOS IOMMU domain as defined in - qti,iommu-hlos-group: Name of the Broadcast HLOS IOMMU domain as defined in <target>-iommu-domains.dtsi, (e.g. mpq8092-iommu-domains.dtsi). The Broadcast HLOS IOMMU domain includes a context bank and virtual address pools definitions, used for mapping non-secured pipe memory buffers. - qcom,iommu-hlos-partition: Partition number in the HLOS IOMMU domain. - qcom,iommu-cpz-group: Name of the Broadcast CPZ IOMMU domain as defined in - qti,iommu-hlos-partition: Partition number in the HLOS IOMMU domain. - qti,iommu-cpz-group: Name of the Broadcast CPZ IOMMU domain as defined in <target>-iommu-domains.dtsi, (e.g. mpq8092-iommu-domains.dtsi). The Broadcast CPZ IOMMU domain includes a context bank and virtual address pool definitions, used for mapping secured pipe memory buffers. - qcom,iommu-cpz-partition: Partition number in the CPZ IOMMU domain. - qti,iommu-cpz-partition: Partition number in the CPZ IOMMU domain. Example (for MPQ8092 platform, avaialble at mpq8092.dtsi): Loading Loading @@ -79,10 +79,10 @@ Example (for MPQ8092 platform, avaialble at mpq8092.dtsi): <96 512 0 0>, /* No vote */ <96 512 1024 1024>, /* Register access only. 8Mbps should be more than enough */ <96 512 24576 61440>; /* Max. bandwidth required is 480Mbps */ qcom,iommu-hlos-group = "bcast_hlos"; qcom,iommu-hlos-partition = <0>; qcom,iommu-cpz-group = "bcast_cpz"; qcom,iommu-cpz-partition = <0>; qti,iommu-hlos-group = "bcast_hlos"; qti,iommu-hlos-partition = <0>; qti,iommu-cpz-group = "bcast_cpz"; qti,iommu-cpz-partition = <0>; };
Documentation/devicetree/bindings/iommu/msm_iommu_v0.txt +18 −18 Original line number Diff line number Diff line Loading @@ -2,27 +2,27 @@ Required properties: - compatible : one of: - "qcom,msm-smmu-v0" - "qti,msm-smmu-v0" - reg : offset and length of the register set for the device. - qcom,glb-offset : Offset for the global register base. - qti,glb-offset : Offset for the global register base. Optional properties: - interrupts : should contain the performance monitor overflow interrupt number. - qcom,iommu-pmu-ngroups: Number of Performance Monitor Unit (PMU) groups. - qcom,iommu-pmu-ncounters: Number of PMU counters per group. - qcom,iommu-pmu-event-classes: List of event classes supported. - qcom,needs-alt-core-clk : boolean to enable the secondary core clock for - qti,iommu-pmu-ngroups: Number of Performance Monitor Unit (PMU) groups. - qti,iommu-pmu-ncounters: Number of PMU counters per group. - qti,iommu-pmu-event-classes: List of event classes supported. - qti,needs-alt-core-clk : boolean to enable the secondary core clock for access to the IOMMU configuration registers - Bus scaling properties: See msm_bus.txt - qcom,msm-enable-remote-spinlock : boolean to enable use of remote spinlock - qti,msm-enable-remote-spinlock : boolean to enable use of remote spinlock - List of sub nodes, one for each of the translation context banks supported. Required properties for each sub-node: - compatible : "qcom,msm-smmu-v0-ctx" - compatible : "qti,msm-smmu-v0-ctx" - reg : offset and length of the register set for the context bank. - interrupts : should contain the context bank interrupt. - qcom,iommu-ctx-mids : List of machine identifiers associated with this - qti,iommu-ctx-mids : List of machine identifiers associated with this translation context. - label : Name of the context bank Loading @@ -31,23 +31,23 @@ Optional properties: Example: qcom,iommu@fd000000 { compatible = "qcom,msm-smmu-v0"; qti,iommu@fd000000 { compatible = "qti,msm-smmu-v0"; #address-cells = <1>; #size-cells = <1>; ranges; reg = <0xfd890000 0x10000>; qcom,glb-offset = <0xF000>; qti,glb-offset = <0xF000>; interrupts = <0 38 0>; qcom,iommu-pmu-ngroups = <1>; qcom,iommu-pmu-ncounters = <4>; qcom,iommu-pmu-event-classes = <0x08 qti,iommu-pmu-ngroups = <1>; qti,iommu-pmu-ncounters = <4>; qti,iommu-pmu-event-classes = <0x08 0x11>; qcom,iommu-ctx@fd000000 { compatible = "qcom,msm-smmu-v0-ctx"; qti,iommu-ctx@fd000000 { compatible = "qti,msm-smmu-v0-ctx"; reg = <0xfd000000 0x1000>; interrupts = <0 250 0>; qcom,iommu-ctx-mids = <0 3>; qti,iommu-ctx-mids = <0 3>; label = "a_label"; };
Documentation/devicetree/bindings/iommu/msm_iommu_v1.txt +33 −33 Original line number Diff line number Diff line Loading @@ -2,7 +2,7 @@ Required properties: - compatible : one of: - "qcom,msm-smmu-v1" - "qti,msm-smmu-v1" - reg : offset and length of the register set for the device. Optional offset and length for clock register for additional clock that needs to be turned on for access to this IOMMU. Loading @@ -10,11 +10,11 @@ Required properties: - label: name of this IOMMU instance. Optional properties: - qcom,iommu-secure-id : Secure identifier for the IOMMU block - qcom,secure-context : boolean indicating that a context is secure and - qti,iommu-secure-id : Secure identifier for the IOMMU block - qti,secure-context : boolean indicating that a context is secure and programmed by the secure environment. - qcom,vdd-supply: Regulator needed to access IOMMU - qcom,alt-vdd-supply : Alternative regulator needed to access IOMMU - qti,vdd-supply: Regulator needed to access IOMMU - qti,alt-vdd-supply : Alternative regulator needed to access IOMMU configuration registers. - interrupts : Interrupt numbers for permormance and global fault interrupts - interrupt-names: Refers to the interrupts number mentioned above. Loading @@ -23,77 +23,77 @@ Optional properties: "global_client_NS_irq" : the global client non-secure interrupt number "global_cfg_S_irq" : the global config secure interrupt number "global_client_S_irq" : the global client secure interrupt number - qcom,iommu-enable-halt : Enable halt of the IOMMU before programming certain 19 - qti,iommu-enable-halt : Enable halt of the IOMMU before programming certain 19 registers - qcom,iommu-pmu-ngroups: Number of Performance Monitor Unit (PMU) groups. - qcom,iommu-pmu-ncounters: Number of PMU counters per group. - qcom,iommu-pmu-event-classes: List of event classes supported. - qti,iommu-pmu-ngroups: Number of Performance Monitor Unit (PMU) groups. - qti,iommu-pmu-ncounters: Number of PMU counters per group. - qti,iommu-pmu-event-classes: List of event classes supported. - Bus scaling properties: See msm_bus.txt - List of sub nodes, one for each of the translation context banks supported. Each sub node has the following required properties: - compatible : "qcom,msm-smmu-v1-ctx" - compatible : "qti,msm-smmu-v1-ctx" - reg : offset and length of the register set for the context bank. - interrupts : should contain the context bank interrupt. If this is a secure context bank, this should be a list of 2 3-tuples where the first is the non-secure interrupt, and the second is the secure interrupt. - qcom,iommu-ctx-sids : List of stream identifiers associated with this - qti,iommu-ctx-sids : List of stream identifiers associated with this translation context. - label : Name of the context bank - vdd-supply : vdd-supply: phandle to GDSC regulator controlling this IOMMU. Optional properties: - qcom,needs-alt-core-clk : boolean to enable the secondary core clock for - qti,needs-alt-core-clk : boolean to enable the secondary core clock for access to the IOMMU configuration registers - qcom,needs-alt-iface-clk : boolean to enable the secondary iface clock for - qti,needs-alt-iface-clk : boolean to enable the secondary iface clock for access to the IOMMU configuration registers - qcom,iommu-bfb-regs : An array of unsigned 32-bit integers corresponding to - qti,iommu-bfb-regs : An array of unsigned 32-bit integers corresponding to BFB register addresses that need to be configured for performance tuning purposes. If this property is present, the qcom,iommu-bfb-data must also be purposes. If this property is present, the qti,iommu-bfb-data must also be present. Register addresses are specified as an offset from the base of the IOMMU hardware block. This property may be omitted if no BFB register configuration needs to be done for a particular IOMMU hardware instance. The registers specified by this property shall fall within the IOMMU implementation-defined register region. - qcom,iommu-bfb-data : An array of unsigned 32-bit integers representing the - qti,iommu-bfb-data : An array of unsigned 32-bit integers representing the values to be programmed into the corresponding registers given by the qcom,iommu-bfb-regs property. If this property is present, the qcom,iommu-bfb-regs property shall also be present, and the lengths of both qti,iommu-bfb-regs property. If this property is present, the qti,iommu-bfb-regs property shall also be present, and the lengths of both properties shall be the same. - qcom,iommu-lpae-bfb-regs : See description for qcom,iommu-bfb-regs. This is - qti,iommu-lpae-bfb-regs : See description for qti,iommu-bfb-regs. This is the same property except this is for IOMMU with LPAE support. - qcom,iommu-lpae-bfb-data : See description for qcom,iommu-bfb-data. This is - qti,iommu-lpae-bfb-data : See description for qti,iommu-bfb-data. This is the same property except this is for IOMMU with LPAE support. Example: qcom,iommu@fda64000 { compatible = "qcom,msm-smmu-v1"; qti,iommu@fda64000 { compatible = "qti,msm-smmu-v1"; reg = <0xfda64000 0x10000>; reg-names = "iommu_base"; vdd-supply = <&gdsc_iommu>; qcom,iommu-bfb-regs = <0x204c 0x2050>; qcom,iommu-bfb-data = <0xffff 0xffce>; qti,iommu-bfb-regs = <0x204c 0x2050>; qti,iommu-bfb-data = <0xffff 0xffce>; label = "iommu_0"; qcom,iommu-pmu-ngroups = <1>; qcom,iommu-pmu-ncounters = <8>; qcom,iommu-pmu-event-classes = <0x00, qti,iommu-pmu-ngroups = <1>; qti,iommu-pmu-ncounters = <8>; qti,iommu-pmu-event-classes = <0x00, 0x01>; qcom,iommu-ctx@fda6c000 { compatible = "qcom,msm-smmu-v1-ctx"; qti,iommu-ctx@fda6c000 { compatible = "qti,msm-smmu-v1-ctx"; reg = <0xfda6c000 0x1000>; interrupts = <0 70 0>; qcom,iommu-ctx-sids = <0 2>; qti,iommu-ctx-sids = <0 2>; label = "ctx_0"; }; qcom,iommu-ctx@fda6d000 { compatible = "qcom,msm-smmu-v1-ctx"; qti,iommu-ctx@fda6d000 { compatible = "qti,msm-smmu-v1-ctx"; reg = <0xfda6d000 0x1000>; interrupts = <0 71 0>; qcom,iommu-ctx-sids = <1>; qti,iommu-ctx-sids = <1>; label = "ctx_1"; }; };
arch/arm/boot/dts/qti/apq8084-iommu-domains.dtsi +23 −23 Original line number Diff line number Diff line Loading @@ -11,49 +11,49 @@ */ &soc { qcom,iommu-domains { compatible = "qcom,iommu-domains"; qti,iommu-domains { compatible = "qti,iommu-domains"; qcom,iommu-domain1 { qti,iommu-domain1 { label = "lpass_secure"; qcom,iommu-contexts = <&lpass_q6_fw>; qcom,virtual-addr-pool = <0x00000000 0x0FFFFFFF qti,iommu-contexts = <&lpass_q6_fw>; qti,virtual-addr-pool = <0x00000000 0x0FFFFFFF 0xF0000000 0x0FFFFFFF>; }; qcom,iommu-domain2 { qti,iommu-domain2 { label = "lpass_audio"; qcom,iommu-contexts = <&lpass_audio_shared qti,iommu-contexts = <&lpass_audio_shared &lpass_core_audio>; qcom,virtual-addr-pool = <0x10000000 0x0FFFFFFF>; qti,virtual-addr-pool = <0x10000000 0x0FFFFFFF>; }; venus_domain_ns: qcom,iommu-domain3 { venus_domain_ns: qti,iommu-domain3 { label = "venus_ns"; qcom,iommu-contexts = <&venus_ns>; qcom,virtual-addr-pool = <0x5dc00000 0x7f000000 qti,iommu-contexts = <&venus_ns>; qti,virtual-addr-pool = <0x5dc00000 0x7f000000 0xdcc00000 0x1000000>; }; venus_domain_sec_bitstream: qcom,iommu-domain4 { venus_domain_sec_bitstream: qti,iommu-domain4 { label = "venus_sec_bitstream"; qcom,iommu-contexts = <&venus_sec_bitstream>; qcom,virtual-addr-pool = <0x4b000000 0x12c00000>; qcom,secure-domain; qti,iommu-contexts = <&venus_sec_bitstream>; qti,virtual-addr-pool = <0x4b000000 0x12c00000>; qti,secure-domain; }; venus_domain_sec_pixel: qcom,iommu-domain5 { venus_domain_sec_pixel: qti,iommu-domain5 { label = "venus_sec_pixel"; qcom,iommu-contexts = <&venus_sec_pixel>; qcom,virtual-addr-pool = <0x25800000 0x25800000>; qcom,secure-domain; qti,iommu-contexts = <&venus_sec_pixel>; qti,virtual-addr-pool = <0x25800000 0x25800000>; qti,secure-domain; }; venus_domain_sec_non_pixel: qcom,iommu-domain6 { venus_domain_sec_non_pixel: qti,iommu-domain6 { label = "venus_sec_non_pixel"; qcom,iommu-contexts = <&venus_sec_non_pixel>; qcom,virtual-addr-pool = <0x1000000 0x24800000>; qcom,secure-domain; qti,iommu-contexts = <&venus_sec_non_pixel>; qti,virtual-addr-pool = <0x1000000 0x24800000>; qti,secure-domain; }; }; };
