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Commit 818ff9aa authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Enable SPI on msmzirc"

parents 5bfbddc6 92d77f7e

arch/arm/boot/dts/qcom/msmzirc-pinctrl.dtsi

+2 −20
Original line number Diff line number Diff line
@@ -80,7 +80,7 @@ 
			/* MOSI, MISO, CLK */

			qcom,pins = <&gp 0>, <&gp 1>, <&gp 3>;

			qcom,num-grp-pins = <3>;

			qcom,pin-func = <1>;

			qcom,pin-func = <2>;

			label = "spi0-active";

			/* active state */

			spi0_default: default {
@@ -106,7 +106,7 @@ 
			/* CS */

			qcom,pins = <&gp 2>;

			qcom,num-grp-pins = <1>;

			qcom,pin-func = <1>;

			qcom,pin-func = <2>;

			label = "spi0-cs0-active";

			spi0_cs0_active: cs0_active {

				drive-strength = <2>;
@@ -779,24 +779,6 @@ 
			};

		};



		pmx_i2c_2 {

			/* CLK, DATA */

			qcom,pins = <&gp 6>, <&gp 7>;

			qcom,num-grp-pins = <2>;

			qcom,pin-func = <3>;

			label = "pmx_i2c_2";



			i2c_2_active: i2c_2_active {

				drive-strength = <2>; /* 2 MA */

				bias-disable = <0>; /* No PULL */

			};



			i2c_2_sleep: i2c_2_sleep {

				drive-strength = <2>; /* 2 MA */

				bias-disable = <0>; /* No PULL */

			};

		};



		pmx_i2c_3 {

			qcom,pins = <&gp 10>, <&gp 11>;

			qcom,num-grp-pins = <2>;

arch/arm/boot/dts/qcom/msmzirc.dtsi

+1 −28
Original line number Diff line number Diff line
@@ -28,7 +28,6 @@ 
		smd36 = &smdtty_loopback;

		spi0 = &spi_0;

		spi1 = &spi_1;

		i2c2 = &i2c_2;

		i2c3 = &i2c_3;

		qpic_nand1 = &qnand_1;

	};
@@ -357,7 +356,7 @@ 
		reg = <0x78b6000 0x600>,

		      <0x7884000 0x23000>;

		interrupt-names = "spi_irq", "spi_bam_irq";

		interrupts = <0 96 0>, <0 239 0>;

		interrupts = <0 96 0>, <0 238 0>;

		spi-max-frequency = <50000000>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&spi1_default &spi1_cs0_active>;
@@ -369,32 +368,6 @@ 
		qcom,use-pinctrl;

		qcom,ver-reg-exists;

		qcom,master-id = <86>;

		status = "disabled";

        };



	i2c_2: i2c@78b6000 { /* BLSP1 QUP2 */

		compatible = "qcom,i2c-msm-v2";

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "qup_phys_addr", "bam_phys_addr";

		reg = <0x78b6000 0x1000>,

		      <0x7884000 0x23000>;

		interrupt-names = "qup_irq", "bam_irq";

		interrupts = <0 96 0>, <0 238 0>;

		qcom,clk-freq-out = <100000>;

		qcom,clk-freq-in  = <19200000>;

		clock-names = "iface_clk", "core_clk";

		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,

			 <&clock_gcc clk_gcc_blsp1_qup2_i2c_apps_clk>;



		pinctrl-names = "i2c_active", "i2c_sleep";

		pinctrl-0 = <&i2c_2_active>;

		pinctrl-1 = <&i2c_2_sleep>;

		qcom,noise-rjct-scl = <0>;

		qcom,noise-rjct-sda = <0>;

		qcom,bam-pipe-idx-cons = <6>;

		qcom,bam-pipe-idx-prod = <7>;

		qcom,master-id = <86>;

        };



	i2c_3: i2c@78b7000 { /* BLSP1 QUP3 */