Loading arch/arm/boot/dts/qcom/msm8994.dtsi +39 −8 Original line number Diff line number Diff line Loading @@ -30,8 +30,39 @@ cpus { #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&CPU0>; }; core1 { cpu = <&CPU1>; }; core2 { cpu = <&CPU2>; }; core3 { cpu = <&CPU3>; }; }; cluster1 { core0 { cpu = <&CPU4>; }; core1 { cpu = <&CPU5>; }; core2 { cpu = <&CPU6>; }; core3 { cpu = <&CPU7>; }; }; }; cpu@0 { CPU0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; Loading @@ -39,7 +70,7 @@ qcom,acc = <&acc0>; }; cpu@1 { CPU1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x1>; Loading @@ -47,7 +78,7 @@ qcom,acc = <&acc1>; }; cpu@2 { CPU2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x2>; Loading @@ -55,7 +86,7 @@ qcom,acc = <&acc2>; }; cpu@3 { CPU3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x3>; Loading @@ -63,7 +94,7 @@ qcom,acc = <&acc3>; }; cpu@100 { CPU4: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x100>; Loading @@ -71,7 +102,7 @@ qcom,acc = <&acc4>; }; cpu@101 { CPU5: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x101>; Loading @@ -79,7 +110,7 @@ qcom,acc = <&acc5>; }; cpu@102 { CPU6: cpu@102 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x102>; Loading @@ -87,7 +118,7 @@ qcom,acc = <&acc6>; }; cpu@103 { CPU7: cpu@103 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x103>; Loading Loading
arch/arm/boot/dts/qcom/msm8994.dtsi +39 −8 Original line number Diff line number Diff line Loading @@ -30,8 +30,39 @@ cpus { #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&CPU0>; }; core1 { cpu = <&CPU1>; }; core2 { cpu = <&CPU2>; }; core3 { cpu = <&CPU3>; }; }; cluster1 { core0 { cpu = <&CPU4>; }; core1 { cpu = <&CPU5>; }; core2 { cpu = <&CPU6>; }; core3 { cpu = <&CPU7>; }; }; }; cpu@0 { CPU0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; Loading @@ -39,7 +70,7 @@ qcom,acc = <&acc0>; }; cpu@1 { CPU1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x1>; Loading @@ -47,7 +78,7 @@ qcom,acc = <&acc1>; }; cpu@2 { CPU2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x2>; Loading @@ -55,7 +86,7 @@ qcom,acc = <&acc2>; }; cpu@3 { CPU3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x3>; Loading @@ -63,7 +94,7 @@ qcom,acc = <&acc3>; }; cpu@100 { CPU4: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x100>; Loading @@ -71,7 +102,7 @@ qcom,acc = <&acc4>; }; cpu@101 { CPU5: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x101>; Loading @@ -79,7 +110,7 @@ qcom,acc = <&acc5>; }; cpu@102 { CPU6: cpu@102 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x102>; Loading @@ -87,7 +118,7 @@ qcom,acc = <&acc6>; }; cpu@103 { CPU7: cpu@103 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x103>; Loading