Loading arch/arm/boot/dts/apq8084.dtsi +11 −0 Original line number Diff line number Diff line Loading @@ -2353,6 +2353,17 @@ qcom,firmware-name = "vpu"; }; cpu-pmu { compatible = "qcom,krait-pmu"; qcom,irq-is-percpu; interrupts = <1 7 0xf00>; }; l2-pmu { compatible = "qcom,l2-pmu"; interrupts = <0 1 0>; }; }; &gdsc_venus { Loading arch/arm/mach-msm/perf_debug.c +1 −0 Original line number Diff line number Diff line Loading @@ -32,6 +32,7 @@ static char *descriptions = " 7 Perf: Add L1 counters to tracepoints\n" " 8 Perf: Make per-process counters configurable\n" " 9 msm: perf: Add L2 support for tracecounters\n" "10 ARM: dts: msm: add perf-events support for apq8084\n" ; static ssize_t desc_read(struct file *fp, char __user *buf, Loading Loading
arch/arm/boot/dts/apq8084.dtsi +11 −0 Original line number Diff line number Diff line Loading @@ -2353,6 +2353,17 @@ qcom,firmware-name = "vpu"; }; cpu-pmu { compatible = "qcom,krait-pmu"; qcom,irq-is-percpu; interrupts = <1 7 0xf00>; }; l2-pmu { compatible = "qcom,l2-pmu"; interrupts = <0 1 0>; }; }; &gdsc_venus { Loading
arch/arm/mach-msm/perf_debug.c +1 −0 Original line number Diff line number Diff line Loading @@ -32,6 +32,7 @@ static char *descriptions = " 7 Perf: Add L1 counters to tracepoints\n" " 8 Perf: Make per-process counters configurable\n" " 9 msm: perf: Add L2 support for tracecounters\n" "10 ARM: dts: msm: add perf-events support for apq8084\n" ; static ssize_t desc_read(struct file *fp, char __user *buf, Loading