Merge "msm: kgsl: Reset HLSQ in A4XX snapshot" (800e6419) · Commits · e / devices / android_kernel_sony_msm8994

drivers/gpu/msm/a4xx_reg.h

+2 −1

Original line number	Diff line number	Diff line
		@@ -56,8 +56,8 @@ enum a4xx_rb_perfctr_rb_sel {
		#define A4XX_RBBM_INT_CLEAR_CMD 0x36
		#define A4XX_RBBM_INT_0_MASK 0x37
		#define A4XX_RBBM_RBBM_CTL 0x3e
		#define A4XX_RBBM_BLOCK_SW_RESET_CMD 0x45
		#define A4XX_RBBM_EXT_TRACE_BUS_CTL 0x49

		#define A4XX_RBBM_CFG_DEBBUS_SEL_A 0x4a
		#define A4XX_RBBM_CFG_DEBBUS_SEL_B 0x4b
		#define A4XX_RBBM_CFG_DEBBUS_SEL_C 0x4c
		@@ -562,6 +562,7 @@ enum a4xx_pc_perfctr_pc_sel {
		};

		/* HLSQ registers */
		#define A4XX_HLSQ_TIMEOUT_THRESHOLD 0xe00
		#define A4XX_HLSQ_PERFCTR_HLSQ_SEL_0 0xe06
		#define A4XX_HLSQ_PERFCTR_HLSQ_SEL_1 0xe07
		#define A4XX_HLSQ_PERFCTR_HLSQ_SEL_2 0xe08

drivers/gpu/msm/adreno.h

+3 −0

Original line number	Diff line number	Diff line
		@@ -567,6 +567,9 @@ extern const unsigned int a330_registers_count;
		extern const unsigned int a4xx_registers[];
		extern const unsigned int a4xx_registers_count;

		extern const unsigned int a4xx_sp_tp_registers[];
		extern const unsigned int a4xx_sp_tp_registers_count;

		extern unsigned int ft_detect_regs[];

		int adreno_idle(struct kgsl_device *device);

drivers/gpu/msm/adreno_a3xx_snapshot.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -455,6 +455,7 @@ static void _snapshot_a330_regs(struct kgsl_snapshot_registers *regs,
		/* For A330, append the additional list of new registers to grab */
		regs[list->count].regs = (unsigned int *) a330_registers;
		regs[list->count].count = a330_registers_count;
		regs[list->count].dump = 1;
		list->count++;
		}

		@@ -485,7 +486,7 @@ void a3xx_snapshot(struct adreno_device adreno_dev, void *snapshot,

		/* Store relevant registers in list to snapshot */
		_snapshot_a3xx_regs(regs, &list, a3xx_registers,
		a3xx_registers_count);
		a3xx_registers_count, 1);
		_snapshot_hlsq_regs(regs, &list, adreno_dev);
		if (adreno_is_a330(adreno_dev) \|\| adreno_is_a305b(adreno_dev))
		_snapshot_a330_regs(regs, &list);

drivers/gpu/msm/adreno_a3xx_snapshot.h

+3 −1

Original line number	Diff line number	Diff line
		@@ -42,10 +42,12 @@ int a3xx_snapshot_vpc_memory(struct kgsl_device device, void snapshot,
		static inline void _snapshot_a3xx_regs(struct kgsl_snapshot_registers *regs,
		struct kgsl_snapshot_registers_list *list,
		const unsigned int *registers,
		const unsigned int count)
		const unsigned int count, int dump)
		{
		regs[list->count].regs = (unsigned int *)registers;
		regs[list->count].count = count;
		regs[list->count].dump = dump;
		regs[list->count].snap_addr = NULL;
		list->count++;
		}
		#endif /__A3XX_SNAPSHOT_H /

drivers/gpu/msm/adreno_a4xx.c

+20 −20

Original line number	Diff line number	Diff line
		@@ -39,18 +39,12 @@ const unsigned int a4xx_registers[] = {
		0x0CC0, 0x0CC0, 0x0CC4, 0x0CD2,
		/* PC */
		0x0D00, 0x0D0C, 0x0D10, 0x0D17, 0x0D20, 0x0D23,
		/* HLSQ */
		0x0E00, 0x0E00, 0x0E04, 0x0E0E, 0x0E30, 0x0E30,
		/* VFD */
		0x0E40, 0x0E4A,
		/* VPC */
		0x0E60, 0x0E61, 0x0E63, 0x0E68,
		/* UCHE */
		0x0E80, 0x0E84, 0x0E88, 0x0E95,
		/* SP */
		0x0EC0, 0x0ECF,
		/* TPL1 */
		0x0F00, 0x0F0B,
		/* VMIDMT */
		0x1000, 0x1000, 0x1002, 0x1002, 0x1004, 0x1004, 0x1008, 0x100A,
		0x100C, 0x100D, 0x100F, 0x1010, 0x1012, 0x1016, 0x1024, 0x1024,
		@@ -63,26 +57,12 @@ const unsigned int a4xx_registers[] = {
		0x21C0, 0x21C6, 0x21D0, 0x21D0, 0x21D9, 0x21D9, 0x21E5, 0x21E7,
		/* VFD CTX 0 */
		0x2200, 0x2204, 0x2208, 0x22A9,
		/* SP CTX 0 */
		0x22C0, 0x22C1, 0x22C4, 0x22E5, 0x22E8, 0x22F8, 0x2300, 0x2306,
		0x230C, 0x2312, 0x2318, 0x2339, 0x2340, 0x2360,
		/* TPL1 CTX 0 */
		0x2380, 0x2382, 0x2384, 0x238F, 0x23A0, 0x23A6,
		/* HLSQ CTX 0 */
		0x23C0, 0x23DB,
		/* GRAS CTX 1 */
		0x2400, 0x2404, 0x2408, 0x2467, 0x2470, 0x2478, 0x247B, 0x256E,
		/* PC CTX 1 */
		0x25C0, 0x25C6, 0x25D0, 0x25D0, 0x25D9, 0x25D9, 0x25E5, 0x25E7,
		/* VFD CTX 1 */
		0x2600, 0x2604, 0x2608, 0x26A9,
		/* SP CTX 1 */+
		0x26C0, 0x26C1, 0x26C4, 0x26E5, 0x26E8, 0x26F8, 0x2700, 0x2706,
		0x270C, 0x2712, 0x2718, 0x2739, 0x2740, 0x2760,
		/* TPL1 CTX 1 */
		0x2780, 0x2782, 0x2784, 0x278F, 0x27A0, 0x27A6,
		/* HLSQ CTXT 1 */
		0x27C0, 0x27DB,
		/* XPU */
		0x2C00, 0x2C01, 0x2C10, 0x2C10, 0x2C12, 0x2C16, 0x2C1D, 0x2C20,
		0x2C28, 0x2C28, 0x2C30, 0x2C30, 0x2C32, 0x2C36, 0x2C40, 0x2C40,
		@@ -126,6 +106,26 @@ const unsigned int a4xx_registers[] = {

		const unsigned int a4xx_registers_count = ARRAY_SIZE(a4xx_registers) / 2;

		const unsigned int a4xx_sp_tp_registers[] = {
		/* SP */
		0x0EC0, 0x0ECF,
		/* TPL1 */
		0x0F00, 0x0F0B,
		/* SP CTX 0 */
		0x22C0, 0x22C1, 0x22C4, 0x22E5, 0x22E8, 0x22F8, 0x2300, 0x2306,
		0x230C, 0x2312, 0x2318, 0x2339, 0x2340, 0x2360,
		/* TPL1 CTX 0 */
		0x2380, 0x2382, 0x2384, 0x238F, 0x23A0, 0x23A6,
		/* SP CTX 1 */+
		0x26C0, 0x26C1, 0x26C4, 0x26E5, 0x26E8, 0x26F8, 0x2700, 0x2706,
		0x270C, 0x2712, 0x2718, 0x2739, 0x2740, 0x2760,
		/* TPL1 CTX 1 */
		0x2780, 0x2782, 0x2784, 0x278F, 0x27A0, 0x27A6,
		};

		const unsigned int a4xx_sp_tp_registers_count =
		ARRAY_SIZE(a4xx_sp_tp_registers) / 2;

		/*
		* Define registers for a4xx that contain addresses used by the
		* cp parser logic