Merge "ARM: 8036/1: Enable IRQs before attempting to read user space in __und_usr"

	@

	adr	r9, BSYM(ret_from_exception)

	@ IRQs must be enabled before attempting to read the instruction from

	@ user space since that could cause a page/translation fault if the

	@ page table was modified by another CPU.

	enable_irq

	tst	r3, #PSR_T_BIT			@ Thumb mode?

	bne	__und_usr_thumb

	sub	r4, r2, #4			@ ARM instr at LR - 4

 *  r9  = normal "successful" return address

 *  r10 = this threads thread_info structure

 *  lr  = unrecognised instruction return address

 * IRQs disabled, FIQs enabled.

 * IRQs enabled, FIQs enabled.

 */

	@

	@ Fall-through from Thumb-2 __und_usr

#endif

do_fpe:

	enable_irq

	ldr	r4, .LCfp

	add	r10, r10, #TI_FPSTATE		@ r10 = workspace

	ldr	pc, [r4]			@ Call FP module USR entry point

	b	1f

__und_usr_fault_16:

	mov	r1, #2

1:	enable_irq

	mov	r0, sp

1:	mov	r0, sp

	adr	lr, BSYM(ret_from_exception)

	b	__und_fault

ENDPROC(__und_usr_fault_32)

 * r9  = ret_from_exception

 * lr  = undefined instr exit

 *

 * called from prefetch exception handler with interrupts disabled

 * called from prefetch exception handler with interrupts enabled

 */

ENTRY(iwmmxt_task_enable)

 * r9  = ret_from_exception

 * lr  = undefined instr exit

 *

 * called from prefetch exception handler with interrupts disabled

 * called from prefetch exception handler with interrupts enabled

 */

ENTRY(crunch_task_enable)

	ldr	r8, =(EP93XX_APB_VIRT_BASE + 0x00130000)	@ syscon addr

@  r9  = normal "successful" return address

@  r10 = this threads thread_info structure

@  lr  = unrecognised instruction return address

@  IRQs disabled.

@  IRQs enabled.

@

ENTRY(do_vfp)

#ifdef CONFIG_PREEMPT_COUNT

	add	r11, r4, #1		@ increment it

	str	r11, [r10, #TI_PREEMPT]

#endif

	enable_irq

 	ldr	r4, .LCvfp

	ldr	r11, [r10, #TI_CPU]	@ CPU number

	add	r10, r10, #TI_VFPSTATE	@ r10 = workspace