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Commit 7e6dc812 authored by Vignesh Radhakrishnan's avatar Vignesh Radhakrishnan
Browse files

msm: clock-8092 : Enable UART dummy clock entries for RUMI 



Modified dummy clock entries to support UART on RUMI for 8092

Change-Id: Ibc5d8b8f26d1b41d66901425715645dfba5c9d36
Signed-off-by: default avatarVignesh Radhakrishnan <vigneshr@codeaurora.org>
parent c936945a

arch/arm/mach-msm/clock-8092.c

+4 −4
Original line number Original line Diff line number Diff line
@@ -6041,10 +6041,10 @@ static struct measure_clk measure_clk = { 
 */

 */

static struct clk_lookup mpq_clocks_8092_rumi[] = {

static struct clk_lookup mpq_clocks_8092_rumi[] = {

	CLK_DUMMY("xo",	cxo_pil_lpass_clk.c,	"fe200000.qcom,lpass", OFF),

	CLK_DUMMY("xo",	cxo_pil_lpass_clk.c,	"fe200000.qcom,lpass", OFF),

	CLK_DUMMY("core_clk",	BLSP1_UART_CLK,	"msm_serial_hsl.0", OFF),

	CLK_DUMMY("core_clk",   BLSP1_UART2_CLK, "f991f000.serial", OFF),

	CLK_DUMMY("iface_clk",	BLSP1_UART_CLK,	"msm_serial_hsl.0", OFF),

	CLK_DUMMY("iface_clk",  BLSP1_UART2_CLK, "f991f000.serial", OFF),

	CLK_DUMMY("core_clk",	BLSP1_UART_CLK,	"msm_serial_hsl.1", OFF),

	CLK_DUMMY("core_clk",   BLSP1_UART5_CLK, "f9922000.serial", OFF),

	CLK_DUMMY("iface_clk",	BLSP1_UART_CLK,	"msm_serial_hsl.1", OFF),

	CLK_DUMMY("iface_clk",  BLSP1_UART5_CLK, "f9922000.serial", OFF),

	CLK_DUMMY("core_clk",	SDC1_CLK,	"msm_sdcc.1", OFF),

	CLK_DUMMY("core_clk",	SDC1_CLK,	"msm_sdcc.1", OFF),

	CLK_DUMMY("iface_clk",	SDC1_P_CLK,	"msm_sdcc.1", OFF),

	CLK_DUMMY("iface_clk",	SDC1_P_CLK,	"msm_sdcc.1", OFF),

	CLK_DUMMY("core_clk",	SDC2_CLK,	"msm_sdcc.2", OFF),

	CLK_DUMMY("core_clk",	SDC2_CLK,	"msm_sdcc.2", OFF),