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Commit 7db76efc authored by Srinivas Ramana's avatar Srinivas Ramana
Browse files

ARM: dts: msm: Refactor the device tree files for msm8939 



Refactor the device tree files for msm8939 so that the
support for 8936 can be added easily. Get all common nodes into
common files that can be used on both platforms.

Change-Id: I02f5cd3113f23f3793620ad8e068c0a411bb27e3
Signed-off-by: default avatarSrinivas Ramana <sramana@codeaurora.org>
parent dfc6b80d

arch/arm/boot/dts/qcom/msm8939-cdp-smb1360.dts

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/dts-v1/;



#include "msm8939.dtsi"

#include "msm8939-cdp.dtsi"



/ {

arch/arm/boot/dts/qcom/msm8939-cdp.dts

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@@ -12,6 +12,7 @@ 


/dts-v1/;



#include "msm8939.dtsi"

#include "msm8939-cdp.dtsi"



/ {

arch/arm/boot/dts/qcom/msm8939-cdp.dtsi

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 * GNU General Public License for more details.

 */



#include "msm8939.dtsi"

#include "msm8939-pinctrl.dtsi"

#include "msm8939-camera-sensor-cdp.dtsi"

arch/arm/boot/dts/qcom/msm8939-common.dtsi

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File added.

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arch/arm/boot/dts/qcom/msm8939-cpu.dtsi

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/* Copyright (c) 2014, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



/ {

	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		cpu-map {

			cluster0 {

				core0 {

					cpu = <&CPU4>;

				};

				core1 {

					cpu = <&CPU5>;

				};

				core2 {

					cpu = <&CPU6>;

				};

				core3 {

					cpu = <&CPU7>;

				};

			};



			cluster1 {

				core0 {

					cpu = <&CPU0>;

				};

				core1 {

					cpu = <&CPU1>;

				};

				core2 {

					cpu = <&CPU2>;

				};

				core3 {

					cpu = <&CPU3>;

				};

			};

		};



		CPU0: cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x100>;

			enable-method = "qcom,arm-cortex-acc";

			qcom,acc = <&acc0>;

			next-level-cache = <&L2_1>;

			L2_1: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;

			      power-domain = <&l2ccc_1>;

			};

		};



		CPU1: cpu@101 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x101>;

			enable-method = "qcom,arm-cortex-acc";

			qcom,acc = <&acc1>;

			next-level-cache = <&L2_1>;

		};



		CPU2: cpu@102 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x102>;

			enable-method = "qcom,arm-cortex-acc";

			qcom,acc = <&acc2>;

			next-level-cache = <&L2_1>;

		};



		CPU3: cpu@103 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x103>;

			enable-method = "qcom,arm-cortex-acc";

			qcom,acc = <&acc3>;

			next-level-cache = <&L2_1>;

		};



		CPU4: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0>;

			enable-method = "qcom,arm-cortex-acc";

			qcom,acc = <&acc4>;

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;

			      power-domain = <&l2ccc_0>;

			};

		};



		CPU5: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x1>;

			enable-method = "qcom,arm-cortex-acc";

			qcom,acc = <&acc5>;

			next-level-cache = <&L2_0>;

		};



		CPU6: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x2>;

			enable-method = "qcom,arm-cortex-acc";

			qcom,acc = <&acc6>;

			next-level-cache = <&L2_0>;

		};



		CPU7: cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x3>;

			enable-method = "qcom,arm-cortex-acc";

			qcom,acc = <&acc7>;

			next-level-cache = <&L2_0>;

		};

	};

};



&soc {

	l2ccc_0: clock-controller@b111000 {

		compatible = "qcom,8916-l2ccc";

		reg = <0x0b111000 0x1000>;

	};



	l2ccc_1: clock-controller@b011000 {

		compatible = "qcom,8916-l2ccc";

		reg = <0x0b011000 0x1000>;

	};



	acc0:clock-controller@b088000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b088000 0x1000>;

	};



	acc1:clock-controller@b098000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b098000 0x1000>;

	};



	acc2:clock-controller@b0a8000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b0a8000 0x1000>;

	};



	acc3:clock-controller@b0b8000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b0b8000 0x1000>;

	};



	acc4:clock-controller@b188000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b188000 0x1000>;

	};



	acc5:clock-controller@b198000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b198000 0x1000>;

	};



	acc6:clock-controller@b1a8000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b1a8000 0x1000>;

	};



	acc7:clock-controller@b1b8000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b1b8000 0x1000>;

	};

};