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Commit 798c6930 authored by Dolev Raviv's avatar Dolev Raviv
Browse files

phy: ufs: Add calibration for new version of UFS 20nm PHY 



Different UFS PHY versions may have different calibration values to some
of the registers.
This change introduces the new calibration values necessary for new
version of UFS 20nm PHY

Change-Id: Ie0522c7293944e3f434fdfe56c82b98d8f5e7994
Signed-off-by: default avatarDolev Raviv <draviv@codeaurora.org>
parent 9a3a61a2

drivers/phy/phy-qcom-ufs-qmp-20nm.c

+16 −2
Original line number Diff line number Diff line
@@ -33,10 +33,23 @@ int ufs_qcom_phy_qmp_20nm_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy) 
	struct ufs_qcom_phy_calibration *tbl_A, *tbl_B;

	int tbl_size_A, tbl_size_B;

	int rate = UFS_QCOM_LIMIT_HS_RATE;

	u8 major = ufs_qcom_phy->host_ctrl_rev_major;

	u16 minor = ufs_qcom_phy->host_ctrl_rev_minor;

	u16 step = ufs_qcom_phy->host_ctrl_rev_step;

	int err;



	tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A);

	tbl_A = phy_cal_table_rate_A;

	if ((major == 0x1) && (minor == 0x002) && (step == 0x0000)) {

		tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_1_2_0);

		tbl_A = phy_cal_table_rate_A_1_2_0;

	} else if ((major == 0x1) && (minor == 0x003) && (step == 0x0000)) {

		tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_1_3_0);

		tbl_A = phy_cal_table_rate_A_1_3_0;

	} else {

		dev_err(ufs_qcom_phy->dev, "%s: Unknown UFS-PHY version, no calibration values\n",

			__func__);

		err = -ENODEV;

		goto out;

	}



	tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);

	tbl_B = phy_cal_table_rate_B;
@@ -48,6 +61,7 @@ int ufs_qcom_phy_qmp_20nm_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy) 
		dev_err(ufs_qcom_phy->dev, "%s: ufs_qcom_phy_calibrate() failed %d\n",

			__func__, err);



out:

	return err;

}

drivers/phy/phy-qcom-ufs-qmp-20nm.h

+48 −1
Original line number Diff line number Diff line
@@ -43,6 +43,8 @@ 
#define QSERDES_COM_BGTC			COM_OFF(0xA0)

#define QSERDES_COM_DEC_START1			COM_OFF(0xAC)

#define QSERDES_COM_PLL_AMP_OS			COM_OFF(0xB0)

#define QSERDES_COM_RES_CODE_UP_OFFSET		COM_OFF(0xD8)

#define QSERDES_COM_RES_CODE_DN_OFFSET		COM_OFF(0xDC)

#define QSERDES_COM_DIV_FRAC_START1		COM_OFF(0x100)

#define QSERDES_COM_DIV_FRAC_START2		COM_OFF(0x104)

#define QSERDES_COM_DIV_FRAC_START3		COM_OFF(0x108)
@@ -127,7 +129,7 @@ struct ufs_qcom_phy_qmp_20nm { 
	struct ufs_qcom_phy common_cfg;

};



static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = {

static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_1_2_0[] = {

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_VCOTAIL_EN, 0xe1),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0xcc),
@@ -173,6 +175,51 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = { 
	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(0), 0xdc),

};



static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_1_3_0[] = {

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_VCOTAIL_EN, 0xe1),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0xcc),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL_TXBAND, 0x08),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RXTXEPCLK_EN, 0x10),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x82),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x40),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0xff),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x19),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x90),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL2, 0x03),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(0), 0xf2),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(0), 0x0c),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(0), 0x12),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(1), 0xf2),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(1), 0x0c),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(1), 0x12),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(0), 0xff),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(0), 0xff),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(0), 0xff),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(0), 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(1), 0xff),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(1), 0xff),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(1), 0xff),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(1), 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x2b),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x38),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x3c),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RES_CODE_UP_OFFSET, 0x02),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RES_CODE_DN_OFFSET, 0x02),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x01),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CNTRL, 0x40),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(0), 0x68),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(1), 0x68),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(1), 0xdc),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(0), 0xdc),

};



static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x98),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0x65),